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"nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "9fe8ef128276ee7315e34b763221fe88a6378866", + "description": "mesa: deduplicate initialization of gl_pixelstore_attrib", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "6a52c50a65112678ea513954e2e216008c40bf9e", + "description": "zink: simplify vb masking on bind", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "068973b0697850b90038101668c92a8ac3b6c575", + "description": "zink: set VkExternalMemoryBufferCreateInfo for opaque fds too", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "7fd12a446d09cb2b21311cad09515cad08987051", + "description": "zink: destroy batch states after copy context", + "nominated": true, + "nomination_type": 1, + "resolution": 1, + "main_sha": null, + "because_sha": "b06f6e00fba6e33c28a198a1bb14b89e9dfbb4ae", + "notes": null + }, + { + "sha": "9227d63c19523b58e278a3d1b40fbde27bb53b41", + "description": "anv: Fix Xe KMD userptr unbind", + "nominated": false, + "nomination_type": 1, + "resolution": 4, + "main_sha": null, + "because_sha": "19439624d9fac333bcd046683bf172a89ff16873", + "notes": null + }, + { + "sha": "a56d2b8dad21ec6d9c44a36fc06fe0556b6e66ed", + "description": "zink: Remove interpolateAtSample() when not multi-sampling", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "4bc1bf16252d7a1ad0d3a8df375fca26efabbf58", + "description": "zink: apply zink_shader::uses_sample to fs variant updating", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "b061ab7198bb93ff77aef7c219102b125cd56e8c", + "description": "zink: track whether shaders use load_barycentric_at_sample", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "e1b66f9707c010a4b554b3039649afb13cba61de", + "description": "compiler/types: fix serialization of cooperative matrix", + "nominated": true, + "nomination_type": 1, + "resolution": 1, + "main_sha": null, + "because_sha": "2d0f4f2c17b79830e9780a68bc473718d4abd4ad", + "notes": null + }, + { + "sha": "fc2b61962160c684b865153f5b8035430cce7c66", + "description": "ci/image-tags: re-generate all the images building deqp-runner", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "fcd43ee243883238b7d5aea6c5338218c12fe9aa", + "description": "ci/deqp-runner: fix list of image tags to update", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "2d80f355627422e5e021072ed8eb443f95e81b76", + "description": "ci/deqp-runner: update repo url", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "810586279c1085387a51acb81a5002549727e13e", + "description": "ci/deqp-runner: bring \"install from crate\" & \"install from git\" to feature parity", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "9eb50036d41fd94beaf64b327bbc0bd32e43abdf", + "description": "ci/deqp-runner: set android rust target in the caller (debian/x86_64_test-android.sh)", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "8fd86519a11284d2ff62581096961a9cbb0983c9", + "description": "ci/deqp-runner: do a release build instead of debug", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "4c92084ed970bc8f75ebd1dbeca5fa1b387bebe7", + "description": "anv/trtt: invalidate the TLB after writing TR-TT entries", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "3e5dfd668d09ea260a667003e33a97fd7b954869", + "description": "anv: add an anv_pipe_bits bit to allow invalidating the TLB", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "52ced4008c90693fe242e6be985a4b58b8b5fe2c", + "description": "intel: Drop pre-production steppings", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "80f532a63664c0c37cef5e261be38ebb5dbf5be2", + "description": "venus: fix VkDeviceGroupSubmitInfo cmd counts from feedback", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "577085ef0e7b4a1290612df00485535d6d578ea7", + "description": "zink: update nv baseline", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "cda4ca53b8df9bbb3a4b788ade8b0b7422dc6dc2", + "description": "nvk: Drop nvk_device::pdev", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "4b38ba5d70a4383f03fd0cee783bedf99386be7e", + "description": "nvk: Replace more dev->pdev with nvk_device_physical()", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "9ddaa4ea105a0ee85af76e4eefea68f4787f58c3", + "description": "nvk: Add and use more cmd_buffer_*_cls helpers", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "f55bb91159ecf62874b4afde1660c1a50fbbcbb3", + "description": "nvk: Drop a bunch of dev->pdev and just use pdev", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "4c3582893382af2fd39d98d483d73a966fc76681", + "description": "radv,driconf: Remove active accel struct workaround", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "217072d25f4e5fa2414f0c3f4203c2faf3c8a807", + "description": "radv/rt: Force active leaves for every updateable accel struct", + "nominated": true, + "nomination_type": 0, + "resolution": 0, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "d12984edb8a9de6cfd6ade8201fd229c494880d2", + "description": "ac/nir: fix exporting NGG streamout outputs with implicit PrimId from VS/TES", + "nominated": true, + "nomination_type": 0, + "resolution": 1, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "6d287943d17a662c14dfefc110f073159b2955e0", + "description": "vk/update-aliases: drop VK_ERROR_ prefix substitution", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { "sha": "9a57b1df5395bbcaa6f48ea851860bedc7ceefb9", "description": "driconf: add radv_zero_vram for Crystal Project (1637730)", "nominated": true, @@ -4914,7 +21304,7 @@ "description": "glx: only print zink failure-to-load messages if explicitly requested", "nominated": false, "nomination_type": 3, - "resolution": 4, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null @@ -17644,7 +34034,7 @@ "description": "iris: Wait for drm_xe_exec_queue to be idle before destroying it", "nominated": false, "nomination_type": 3, - "resolution": 4, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null @@ -23554,7 +39944,7 @@ "description": "anv: Fix calculation of syncs required in Xe KMD", "nominated": false, "nomination_type": 3, - "resolution": 4, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null @@ -25284,7 +41674,7 @@ "description": "intel/eu/xe2+: Translate brw_reg fields in REG_SIZE units to physical 512b GRF units during codegen.", "nominated": false, "nomination_type": 3, - "resolution": 4, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff -Nru mesa-24.0.3/VERSION mesa-24.0.5/VERSION --- mesa-24.0.3/VERSION 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/VERSION 2024-04-10 20:17:49.000000000 +0000 @@ -1 +1 @@ -24.0.3 +24.0.5 diff -Nru mesa-24.0.3/debian/changelog mesa-24.0.5/debian/changelog --- mesa-24.0.3/debian/changelog 2024-04-15 12:57:15.000000000 +0000 +++ mesa-24.0.5/debian/changelog 2024-04-15 12:57:18.000000000 +0000 @@ -1,3 +1,34 @@ +mesa (24.0.5-1ubuntu1~bpo24.04.1) noble; urgency=medium + + * No-change backport to noble. + + -- Jeremy Bícha Mon, 15 Apr 2024 08:53:07 -0400 + +mesa (24.0.5-1ubuntu1) noble; urgency=medium + + * Merge from Debian. (LP: #2060009, #2060679) + + -- Timo Aaltonen Fri, 12 Apr 2024 10:12:19 +0300 + +mesa (24.0.5-1) unstable; urgency=medium + + * New upstream release. + + -- Timo Aaltonen Thu, 11 Apr 2024 13:13:09 +0300 + +mesa (24.0.4-1) unstable; urgency=medium + + [ Timo Aaltonen ] + * New upstream release. + * patches: Dropped upstreamed patches. + + [ Fabio Pedretti ] + * control: libllvmspirvlib-*-dev is needed even with rusticl disabled + (Closes: #1061287) + * control: Bump meson build-dep + + -- Timo Aaltonen Fri, 29 Mar 2024 17:59:50 +0200 + mesa (24.0.3-1ubuntu4) noble; urgency=medium * No-change rebuild for CVE-2024-3094 diff -Nru mesa-24.0.3/debian/control mesa-24.0.5/debian/control --- mesa-24.0.3/debian/control 2024-04-15 12:57:15.000000000 +0000 +++ mesa-24.0.5/debian/control 2024-04-15 12:57:18.000000000 +0000 @@ -9,7 +9,7 @@ debhelper-compat (= 13), directx-headers-dev (>= 1.610.0) [linux-amd64 linux-arm64], glslang-tools [amd64 arm64 armel armhf i386 loong64 powerpc ppc64 ppc64el riscv64 s390x sparc64 x32], - meson (>= 0.45), + meson (>= 1.3.1), quilt (>= 0.63-8.2~), pkg-config, libdrm-dev (>= 2.4.119), @@ -57,7 +57,7 @@ bindgen (>= 0.66.1~) [amd64 arm64 armel armhf loong64 powerpc ppc64 ppc64el riscv64 s390x x32], llvm-spirv-17 [amd64 arm64 armel armhf loong64 powerpc ppc64 ppc64el riscv64 s390x x32], libclc-17 [amd64 arm64 armel armhf loong64 powerpc ppc64 ppc64el riscv64 s390x x32], - libllvmspirvlib-17-dev [amd64 arm64 armel armhf loong64 powerpc ppc64 ppc64el riscv64 s390x x32], + libllvmspirvlib-17-dev [amd64 arm64 armel armhf i386 loong64 powerpc ppc64 ppc64el riscv64 s390x sparc64 x32], Rules-Requires-Root: no Vcs-Git: https://salsa.debian.org/xorg-team/lib/mesa.git Vcs-Browser: https://salsa.debian.org/xorg-team/lib/mesa diff -Nru mesa-24.0.3/debian/control.in mesa-24.0.5/debian/control.in --- mesa-24.0.3/debian/control.in 2024-04-15 12:57:15.000000000 +0000 +++ mesa-24.0.5/debian/control.in 2024-04-15 12:57:18.000000000 +0000 @@ -9,7 +9,7 @@ debhelper-compat (= 13), directx-headers-dev (>= 1.610.0) [linux-amd64 linux-arm64], glslang-tools [@LLVM_ARCHS@], - meson (>= 0.45), + meson (>= 1.3.1), quilt (>= 0.63-8.2~), pkg-config, libdrm-dev (>= 2.4.119), @@ -57,7 +57,7 @@ bindgen (>= 0.66.1~) [@RUSTICL_ARCHS@], llvm-spirv-@LLVM_VERSION@ [@RUSTICL_ARCHS@], libclc-@LLVM_VERSION@ [@RUSTICL_ARCHS@], - libllvmspirvlib-@LLVM_VERSION@-dev [@RUSTICL_ARCHS@], + libllvmspirvlib-@LLVM_VERSION@-dev [@LLVM_ARCHS@], Rules-Requires-Root: no Vcs-Git: https://salsa.debian.org/xorg-team/lib/mesa.git Vcs-Browser: https://salsa.debian.org/xorg-team/lib/mesa diff -Nru mesa-24.0.3/debian/patches/fix-zink-logging.diff mesa-24.0.5/debian/patches/fix-zink-logging.diff --- mesa-24.0.3/debian/patches/fix-zink-logging.diff 2024-04-15 12:57:15.000000000 +0000 +++ mesa-24.0.5/debian/patches/fix-zink-logging.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,112 +0,0 @@ -From 79442618bec83eb8d1de8cccb80e2d794b8ac6a6 Mon Sep 17 00:00:00 2001 -From: Mike Blumenkrantz -Date: Tue, 27 Feb 2024 17:05:13 -0500 -Subject: [PATCH 2/2] glx: only print zink failure-to-load messages if - explicitly requested - -if zink is inferred, let it fail silently - -ref #10293 ---- - src/glx/drisw_glx.c | 9 ++++++--- - src/glx/drisw_priv.h | 2 +- - src/glx/glxclient.h | 8 +++++++- - src/glx/glxext.c | 5 +++-- - 4 files changed, 17 insertions(+), 7 deletions(-) - -diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c -index 3d3f75259bc16..cbba547d7ebb3 100644 ---- a/src/glx/drisw_glx.c -+++ b/src/glx/drisw_glx.c -@@ -1001,7 +1001,9 @@ driswCreateScreenDriver(int screen, struct glx_display *priv, - if (!psc->has_multibuffer && - !debug_get_bool_option("LIBGL_ALWAYS_SOFTWARE", false) && - !debug_get_bool_option("LIBGL_KOPPER_DRI2", false)) { -- CriticalErrorMessageF("DRI3 not available\n"); -+ /* only print error if zink was explicitly requested */ -+ if (pdpyp->zink == TRY_ZINK_YES) -+ CriticalErrorMessageF("DRI3 not available\n"); - goto handle_error; - } - } -@@ -1049,7 +1051,8 @@ driswCreateScreenDriver(int screen, struct glx_display *priv, - glx_screen_cleanup(&psc->base); - free(psc); - -- CriticalErrorMessageF("failed to load driver: %s\n", driver); -+ if (pdpyp->zink == TRY_ZINK_YES) -+ CriticalErrorMessageF("failed to load driver: %s\n", driver); - - return NULL; - } -@@ -1079,7 +1082,7 @@ driswDestroyDisplay(__GLXDRIdisplay * dpy) - * display pointer. - */ - _X_HIDDEN __GLXDRIdisplay * --driswCreateDisplay(Display * dpy, bool zink) -+driswCreateDisplay(Display * dpy, enum try_zink zink) - { - struct drisw_display *pdpyp; - -diff --git a/src/glx/drisw_priv.h b/src/glx/drisw_priv.h -index 53674f81a24a4..c7687ebcb63a7 100644 ---- a/src/glx/drisw_priv.h -+++ b/src/glx/drisw_priv.h -@@ -33,7 +33,7 @@ - struct drisw_display - { - __GLXDRIdisplay base; -- bool zink; -+ enum try_zink zink; - }; - - struct drisw_screen -diff --git a/src/glx/glxclient.h b/src/glx/glxclient.h -index e262b4a80face..e4eb3b4145178 100644 ---- a/src/glx/glxclient.h -+++ b/src/glx/glxclient.h -@@ -133,11 +133,17 @@ struct __GLXDRIdrawableRec - int refcount; - }; - -+enum try_zink { -+ TRY_ZINK_NO, -+ TRY_ZINK_INFER, -+ TRY_ZINK_YES, -+}; -+ - /* - ** Function to create and DRI display data and initialize the display - ** dependent methods. - */ --extern __GLXDRIdisplay *driswCreateDisplay(Display * dpy, bool zink); -+extern __GLXDRIdisplay *driswCreateDisplay(Display * dpy, enum try_zink zink); - extern __GLXDRIdisplay *dri2CreateDisplay(Display * dpy); - extern __GLXDRIdisplay *dri3_create_display(Display * dpy); - extern __GLXDRIdisplay *driwindowsCreateDisplay(Display * dpy); -diff --git a/src/glx/glxext.c b/src/glx/glxext.c -index 6cf04d1b7450f..eebdfceeb4c08 100644 ---- a/src/glx/glxext.c -+++ b/src/glx/glxext.c -@@ -918,7 +918,8 @@ __glXInitialize(Display * dpy) - } - #endif /* GLX_USE_DRM */ - if (glx_direct) -- dpyPriv->driswDisplay = driswCreateDisplay(dpy, zink | try_zink); -+ dpyPriv->driswDisplay = driswCreateDisplay(dpy, zink ? TRY_ZINK_YES : -+ try_zink ? TRY_ZINK_INFER : TRY_ZINK_NO); - - #ifdef GLX_USE_WINDOWSGL - if (glx_direct && glx_accel) -@@ -939,7 +940,7 @@ __glXInitialize(Display * dpy) - if (try_zink) { - free(dpyPriv->screens); - dpyPriv->driswDisplay->destroyDisplay(dpyPriv->driswDisplay); -- dpyPriv->driswDisplay = driswCreateDisplay(dpy, false); -+ dpyPriv->driswDisplay = driswCreateDisplay(dpy, TRY_ZINK_NO); - fail = !AllocAndFetchScreenConfigs(dpy, dpyPriv, False); - } - #endif --- -GitLab - diff -Nru mesa-24.0.3/debian/patches/radeon-fix-gnome-shell-crash.diff mesa-24.0.5/debian/patches/radeon-fix-gnome-shell-crash.diff --- mesa-24.0.3/debian/patches/radeon-fix-gnome-shell-crash.diff 2024-04-15 12:57:15.000000000 +0000 +++ mesa-24.0.5/debian/patches/radeon-fix-gnome-shell-crash.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,13 +0,0 @@ -diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c -index 2e1d9c488e2..7979cad75fa 100644 ---- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c -+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c -@@ -729,7 +729,7 @@ bool radeon_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry) - { - struct radeon_bo *bo = container_of(entry, struct radeon_bo, u.slab.entry); - -- return radeon_bo_can_reclaim(NULL, &bo->base); -+ return radeon_bo_can_reclaim(priv, &bo->base); - } - - static void radeon_bo_slab_destroy(void *winsys, struct pb_buffer_lean *_buf) diff -Nru mesa-24.0.3/debian/patches/series mesa-24.0.5/debian/patches/series --- mesa-24.0.3/debian/patches/series 2024-04-15 12:57:15.000000000 +0000 +++ mesa-24.0.5/debian/patches/series 2024-04-15 12:57:18.000000000 +0000 @@ -1,4 +1,2 @@ path_max.diff src_glx_dri_common.h.diff -fix-zink-logging.diff -radeon-fix-gnome-shell-crash.diff diff -Nru mesa-24.0.3/docs/egl.rst mesa-24.0.5/docs/egl.rst --- mesa-24.0.3/docs/egl.rst 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/docs/egl.rst 2024-04-10 20:17:49.000000000 +0000 @@ -1,7 +1,7 @@ EGL === -The current version of EGL in Mesa implements EGL 1.4. More information +The current version of EGL in Mesa implements EGL 1.5. More information about EGL can be found at https://www.khronos.org/egl/. The Mesa's implementation of EGL uses a driver architecture. The main diff -Nru mesa-24.0.3/docs/relnotes/24.0.3.rst mesa-24.0.5/docs/relnotes/24.0.3.rst --- mesa-24.0.3/docs/relnotes/24.0.3.rst 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/docs/relnotes/24.0.3.rst 2024-04-10 20:17:49.000000000 +0000 @@ -19,7 +19,7 @@ :: - TBD. + 77aec9a2a37b7d3596ea1640b3cc53d0b5d9b3b52abed89de07e3717e91bfdbe mesa-24.0.3.tar.xz New features diff -Nru mesa-24.0.3/docs/relnotes/24.0.4.rst mesa-24.0.5/docs/relnotes/24.0.4.rst --- mesa-24.0.3/docs/relnotes/24.0.4.rst 1970-01-01 00:00:00.000000000 +0000 +++ mesa-24.0.5/docs/relnotes/24.0.4.rst 2024-04-10 20:17:49.000000000 +0000 @@ -0,0 +1,220 @@ +Mesa 24.0.4 Release Notes / 2024-03-27 +====================================== + +Mesa 24.0.4 is a bug fix release which fixes bugs found since the 24.0.3 release. + +Mesa 24.0.4 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 24.0.4 implements the Vulkan 1.3 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + 90febd30a098cbcd97ff62ecc3dcf5c93d76f7fa314de944cfce81951ba745f0 mesa-24.0.4.tar.xz + + +New features +------------ + +- None + + +Bug fixes +--------- + +- nvk: dota 2 crashes after ~5 seconds in game +- VAAPI: Incorrect HEVC block size reported with radeonsi +- radv: WWE 2K24 has very quirky DCC issues on RDNA2 +- RUSTICL creating a shared reference to mutable static is discouraged and will become a hard error +- KiCAD 3D Viewer - rounded pads rendered incorrectly (texture mapping or stencil test error) +- OpenSCAD rendering incorrect and inconsistent on radeonsi +- [radv] Half-Life Alyx renders solid black for reflective surfaces +- [RX 7900 XTX] Helldivers 2 cause GPU reset +- radeon: Crash in radeon_bo_can_reclaim_slab +- RV530 renders improperly at non 4:3 resolutions. +- anv: new cooperative matrix failures with CTS 1.3.8.0 +- \`[gfxhub0] no-retry page fault` triggered by \`AMD_TEST=testdmaperf` on gfx90c APU + + +Changes +------- + +Boris Brezillon (1): + +- panvk: Disable global offset on varying and non-VS attribute descriptors + +Caio Oliveira (2): + +- intel/brw: Use helper to create accumulator register +- intel/brw: Fix validation of accumulator register + +Charlie Turner (1): + +- {vulkan,radv,anv}/video: fix issue in H264 scaling lists derivation + +Corentin Noël (2): + +- st_pbo/compute: Use the correct structure type when allocating a specialized key +- zink: Make sure to initialize all the fields of VkMemoryBarrier + +Dave Airlie (1): + +- radv/video: fix h265 decode with unaligned w/h + +David Rosca (1): + +- radv/video: Set maxActiveReferencePictures to 16 for H264/5 + +Eric Engestrom (5): + +- docs: add sha256sum for 24.0.3 +- .pick_status.json: Update to 9b6d6c1d2d0c8a517e974abbf7b75a47a607f6ec +- .pick_status.json: Update to eac703f69128d5aa6879c9becbad627ce08a7920 +- .pick_status.json: Update to 912e203a534be8b70b3ef8bf00294e9c962e385a +- .pick_status.json: Update to c0875d21563257442fd91aab5740248b0fd96a5c + +Faith Ekstrand (2): + +- nir/builder: Correctly handle decl_reg or undef as the first instruction +- nir/gather_types: Support unstructured control-flow + +Francisco Jerez (1): + +- intel/eu/xe2+: Translate brw_reg fields in REG_SIZE units to physical 512b GRF units during codegen. + +Friedrich Vock (2): + +- radv: Only enable SEs that the device reports +- radeonsi: Only enable SEs that the device reports + +Gert Wollny (2): + +- nir-to-spirv: Cast SSBO input pointer when needed +- nir_to_spirv: Allow LOD for external images + +Hyunjun Ko (1): + +- anv/video: fix scan order for scaling lists on H265 decoding. + +Iván Briano (2): + +- compiler/types: fix serialization of cooperative matrix +- intel/cmat: fix stride calculation in cmat load/store + +Jordan Justen (1): + +- intel/compiler/fs: Restore SIMD32 restriction for ray_queries on Xe2 + +Karol Herbst (2): + +- rusticl/kernel: assign sampler locations before DCEing variables +- nouveau: call glsl_type_singleton_init_or_ref earlier + +Kenneth Graunke (1): + +- intel/brw: Fix opt_split_sends() to allow for FIXED_GRF send sources + +Konstantin Seurer (1): + +- zink: Handle aoa derefs of images + +Lionel Landwerlin (6): + +- intel/fs: fixup sampler header message +- anv: return unsupported for FSR images on Gfx12.0 +- anv: ignore descriptor alignment for inline uniforms +- blorp: handle a few allocation failure cases +- anv: fix block pool allocation failure +- anv: fix bitfield checks in gfx runtime flushing + +Lucas Stach (1): + +- etnaviv: fix fixpoint conversion of negative values + +Marek Olšák (8): + +- amd/registers: add correct gfx11.x enums for BINNING_MODE +- radeonsi: disable binning correctly on gfx11.5 +- radeonsi/gfx11: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT +- radeonsi/gfx10.3: add a GPU hang workaround for legacy tess+GS +- radeonsi/gfx11: add missing DCC_RD_POLICY setting +- ac/llvm: fix SSBO bounds checking by using raw instead of struct opcodes +- radeonsi: fix the DMA compute shader +- r300: port scanout pitch alignment from the DDX to fix DRI3 + +Mary Guillemard (1): + +- nvk: Always copy conditional rendering value before compare + +Matthew Waters (1): + +- teximage: allow glCopyTex{Sub}Image[123]D into R/RG textures with OpenGL ES 2.0 + +Mike Blumenkrantz (13): + +- zink: destroy batch states after copy context +- mesa: force rendertarget usage on required-renderable formats +- zink: try getting sparse page size again without storage bit on fail +- zink: set the sparse format usage flags directly based on queried props +- zink: rename optimal_key in update_gfx_program_optimal() +- zink: use the sanitized key in update_gfx_program_optimal() +- zink: always sync and replace separable progs even with ZINK_DEBUG=noopt +- zink: add even more strict checks for separate shader usage +- glx: only print zink failure-to-load messages if explicitly requested +- zink: iterate all the modes when doing separate shader fixups +- zink: do io fixup on patch variables too +- zink: defer present barrier to flush if a clear is pending +- zink: clamp swapchain renderarea instead of asserting + +Patrick Lerda (1): + +- ac/llvm,radeonsi: fix memory leaks triggered by ac_nir_translate() errors + +Paulo Zanoni (1): + +- anv: don't leak device->vma_samplers + +Philipp Zabel (1): + +- rusticl: work around reference-to-mutable-static warnings + +Pierre-Eric Pelloux-Prayer (2): + +- winsys/radeon: pass priv instead NULL to radeon_bo_can_reclaim +- radeonsi: preserve alpha if needed in kill_ps_outputs_cb + +Rhys Perry (4): + +- aco: don't reuse misaligned attribute destination VGPRs in VS prologs +- radv: use dual_color_blend_by_location with Half-Life Alyx +- aco/cssa: reset equal_anc_out if merging fails +- aco/gfx11: fix scratch ST mode assembly + +Ruijing Dong (3): + +- radeonsi/vcn: add enc surface alignment caps +- frontends/va: add surface alignment attribute +- radeonsi/vcn: update to use correct padding size. + +Samuel Pitoiset (7): + +- ac/nir: fix exporting NGG streamout outputs with implicit PrimId from VS/TES +- radv: disable binning correctly on GFX11.5 +- radv: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT on GFX11 +- radv: fix occlusion queries with MSAA and no attachments +- radv: add radv_force_pstate_peak_gfx11_dgpu and enable it for Helldivers 2 +- radv: add a workaround for null IBO on GFX6 +- radv: invalidate L2 metadata for VK_ACCESS_2_MEMORY_READ_BIT + +Yusuf Khan (1): + +- nvk: fix valve segfault from setting a descriptor set from NULL diff -Nru mesa-24.0.3/docs/relnotes/24.0.5.rst mesa-24.0.5/docs/relnotes/24.0.5.rst --- mesa-24.0.3/docs/relnotes/24.0.5.rst 1970-01-01 00:00:00.000000000 +0000 +++ mesa-24.0.5/docs/relnotes/24.0.5.rst 2024-04-10 20:17:49.000000000 +0000 @@ -0,0 +1,212 @@ +Mesa 24.0.5 Release Notes / 2024-04-10 +====================================== + +Mesa 24.0.5 is a bug fix release which fixes bugs found since the 24.0.4 release. + +Mesa 24.0.5 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 24.0.5 implements the Vulkan 1.3 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + TBD. + + +New features +------------ + +- None + + +Bug fixes +--------- + +- anv: vkd3d-proton test_stress_suballocation failure +- d3d12: Zwift renders with bad textures/lighting +- NVK: Misrendering with Civilization 6 +- radv: RDR2 might need zerovram +- Issues rendering gtk4 window decorations on v3d on Fedora-40/mesa-24.0 +- clc: Failure when linking with llvm+clang 18.1 (-Dshared-llvm=disabled) +- LLVM-18 build issue + + +Changes +------- + +Axel Davy (5): + +- frontend/nine: Fix ff ps key +- frontend/nine: Fix programmable vs check +- frontend/nine: Fix missing light flag check +- frontend/nine: Fix destruction race +- frontend/nine: Reset should EndScene + +Connor Abbott (2): + +- freedreno/a7xx: Add CP_CCHE_INVALIDATE +- tu: Implement CCHE invalidation + +Dave Airlie (1): + +- mesa: reorder st context teardown + +David Heidelberg (7): + +- r300: add missing licence to the r300_public.h +- r300: add missing copyright header +- docs: we support EGL 1.5 for a long time +- ci/amd: drop old PIGLIT_REPLAY_DESCRIPTION_FILE surpassed by PIGLIT_TRACES_FILE +- r600: add license header to r600_formats.h +- r600: add license info to the r600_opcodes.h +- r600: add license information to the sfn_shader_gs.h + +David Stern (1): + +- vulkan/wsi/x11: Explicitly discard errors from xcb_present_pixmap. + +Eric Engestrom (5): + +- docs: add sha256sum for 24.0.4 +- .pick_status.json: Update to 3d68dd78d07b30cefe90d76af681075f4ed6b33d +- .pick_status.json: Update to fcb568a5d5a52db75fa2f6d04579bb404ca7f597 +- .pick_status.json: Update to 078fe5454e97d073feb18bcdcf7ed1874e8b4835 +- .pick_status.json: Update to 2c1cb65949933a05eedb2eacc15cd893ecaef8aa + +Eric R. Smith (2): + +- panfrost: mark indirect compute buffer as read +- gallium: handle copy_image of depth textures + +Faith Ekstrand (2): + +- nvk: Add a _pad field to nvk_cbuf +- nvk: Add a _pad field to nvk_fs_key + +Georg Lehmann (2): + +- aco: don't combine mul+add_clamp to mad_clamp +- aco/ra: use SDWA for 16bit instructions when the second byte is blocked + +Iago Toral Quiroga (2): + +- v3d: implement fix for GFXH-1602 +- broadcom/compiler: fix workaround for GFXH-1602 + +Ian Romanick (3): + +- intel/brw: Clear write_accumulator flag when changing the destination +- intel/brw: Use enums for DPAS source regioning +- nir: intel/brw: Change the order of sources for nir_dpas_intel + +Jesse Natalie (1): + +- glsl: Use a stable attr sort for VS in / FS out + +Jordan Justen (1): + +- intel/dev: Add 0x56be and 0x56bf DG2 PCI IDs + +José Roberto de Souza (4): + +- anv: Fix calculation of syncs required in Xe KMD +- iris: Wait for drm_xe_exec_queue to be idle before destroying it +- anv: Create protected engine context when i915 supports vm control +- intel: Enable Xe KMD support by default + +Juston Li (1): + +- Revert "zink: store last pipeline directly for zink_gfx_program::last_pipeline" + +Karol Herbst (1): + +- meson: fix link failure with llvm-18 + +Kenneth Graunke (2): + +- intel/brw: Fix generate_mov_indirect to check has_64bit_int not float +- intel/brw: Fix lower_regioning for BROADCAST, MOV_INDIRECT on Q types + +Konstantin Seurer (1): + +- nir/serialize: Encode data for temporaries + +Lionel Landwerlin (7): + +- anv: fix protected memory allocations +- anv: disable protected content around surface state copies +- anv: disable generated draws in protected command buffers +- anv: update protection fault property +- anv: add missing data flush out of L3 for transform feedback writes +- anv: mark descriptors & pipeline dirty after blorp compute +- isl: set NullPageCoherencyEnable for depth/stencil sparse surfaces + +Lucas Stach (2): + +- etnaviv: fix depth writes without testing +- etnaviv: rs: take src dimensions into account when increasing height alignment + +Mike Blumenkrantz (12): + +- zink: only check that CUBE_COMPATIBLE for images doesn't subtract flags +- zink: don't use set_foreach_remove with dmabuf_exports +- zink: make descriptor pool creation more robust +- zink: fix shaderdb pipeline compile +- zink: don't clobber indirect array reads with missing components +- zink: fix add_derefs case for compact arrays +- llvmpipe: fix DRAW_USE_LLVM=0 +- glsl: handle xfb resources for spirv before running varying opts +- mesa: clamp binary pointer in ShaderBinary if length==0 +- glsl: set PSIZ bit in outputs_written when injecting a 1.0 psiz write +- nir/lower_clamp_color_outputs: fix use with lowered io +- nir/texcoord_replace: fix scalarized io handling + +Nikita Popov (1): + +- Pass no-verify-fixpoint option to instcombine in LLVM 18 + +Patrick Lerda (1): + +- r300: fix constants_remap_table memory leak related to the dummy shader path + +Paul Gofman (3): + +- glsl: allow out arrays in #110 with allow_glsl_120_subset_in_110 +- driconf: add a workaround for Joe Danger 2 +- driconf: add a workaround for Joe Danger + +Paulo Zanoni (2): + +- anv/xe: don't leak xe_syncs during trtt submission +- anv, iris: add missing CS_STALL bit for GPGPU texture invalidation + +Samuel Pitoiset (3): + +- radv: fix conditional rendering with mesh+task and multiview (again) +- radv: enable radv_zero_vram for Red Dead Redemption 2 +- radv: make sure the heap budget is less than or equal to the heap size + +Tapani Pälli (1): + +- anv: disable fcv optimization on >= gfx125 + +Yonggang Luo (1): + +- util: Fixes futex_wait on win32 + +Zack Rusin (1): + +- svga: Fix instanced draw detection + +Zan Dobersek (1): + +- tu: fix memory leaks in tu_shader diff -Nru mesa-24.0.3/docs/relnotes.rst mesa-24.0.5/docs/relnotes.rst --- mesa-24.0.3/docs/relnotes.rst 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/docs/relnotes.rst 2024-04-10 20:17:49.000000000 +0000 @@ -3,6 +3,8 @@ The release notes summarize what's new or changed in each Mesa release. +- :doc:`24.0.5 release notes ` +- :doc:`24.0.4 release notes ` - :doc:`24.0.3 release notes ` - :doc:`24.0.2 release notes ` - :doc:`24.0.1 release notes ` @@ -411,6 +413,8 @@ :maxdepth: 1 :hidden: + 24.0.5 + 24.0.4 24.0.3 24.0.2 24.0.1 diff -Nru mesa-24.0.3/include/pci_ids/iris_pci_ids.h mesa-24.0.5/include/pci_ids/iris_pci_ids.h --- mesa-24.0.3/include/pci_ids/iris_pci_ids.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/include/pci_ids/iris_pci_ids.h 2024-04-10 20:17:49.000000000 +0000 @@ -251,6 +251,8 @@ CHIPSET(0x56bb, dg2_g11, "DG2", "Intel(R) Graphics") CHIPSET(0x56bc, dg2_g11, "DG2", "Intel(R) Graphics") CHIPSET(0x56bd, dg2_g11, "DG2", "Intel(R) Graphics") +CHIPSET(0x56be, dg2_g10, "DG2", "Intel(R) Graphics") +CHIPSET(0x56bf, dg2_g10, "DG2", "Intel(R) Graphics") CHIPSET(0x56c0, atsm_g10, "ATS-M", "Intel(R) Data Center GPU Flex Series 170 Graphics") CHIPSET(0x56c1, atsm_g11, "ATS-M", "Intel(R) Data Center GPU Flex Series 140 Graphics") diff -Nru mesa-24.0.3/meson.build mesa-24.0.5/meson.build --- mesa-24.0.3/meson.build 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/meson.build 2024-04-10 20:17:49.000000000 +0000 @@ -1523,11 +1523,6 @@ pre_args += '-DSUPPORT_INTEL_INTEGRATED_GPUS' endif -if get_option('intel-xe-kmd').enabled() - pre_args += '-DINTEL_XE_KMD_SUPPORTED' -endif - - if with_gallium_i915 and host_machine.cpu_family().startswith('x86') == false error('Intel "i915" Gallium driver requires x86 or x86_64 CPU family') endif @@ -1722,7 +1717,7 @@ # all-targets is needed to support static linking LLVM build with multiple targets. # windowsdriver is needded with LLVM>=15 and frontendhlsl is needed with LLVM>=16, # but we don't know what LLVM version we are using yet - llvm_optional_modules += ['all-targets', 'windowsdriver', 'frontendhlsl'] + llvm_optional_modules += ['all-targets', 'windowsdriver', 'frontendhlsl', 'frontenddriver'] endif draw_with_llvm = get_option('draw-use-llvm') if draw_with_llvm @@ -1866,6 +1861,9 @@ if dep_llvm.version().version_compare('>= 16.0') clang_modules += 'clangASTMatchers' endif + if dep_llvm.version().version_compare('>= 18.0') + clang_modules += 'clangAPINotes' + endif dep_clang = [] foreach m : clang_modules diff -Nru mesa-24.0.3/meson_options.txt mesa-24.0.5/meson_options.txt --- mesa-24.0.3/meson_options.txt 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/meson_options.txt 2024-04-10 20:17:49.000000000 +0000 @@ -682,11 +682,4 @@ description : 'Build custom xmlconfig (driconf) support. If disabled, ' + 'the default driconf file is hardcoded into Mesa. ' + 'Requires expat.' -) - -option ( - 'intel-xe-kmd', - type : 'feature', - value : 'disabled', - description: 'Enable Intel Xe KMD support.' -) +) \ No newline at end of file diff -Nru mesa-24.0.3/src/amd/ci/gitlab-ci.yml mesa-24.0.5/src/amd/ci/gitlab-ci.yml --- mesa-24.0.3/src/amd/ci/gitlab-ci.yml 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/ci/gitlab-ci.yml 2024-04-10 20:17:49.000000000 +0000 @@ -46,7 +46,6 @@ variables: EGL_PLATFORM: surfaceless PIGLIT_TRACES_FILE: traces-amd.yml - PIGLIT_REPLAY_DESCRIPTION_FILE: "/install/traces-amd.yml" PIGLIT_REPLAY_EXTRA_ARGS: --keep-image radv-raven-vkcts:x86_64: diff -Nru mesa-24.0.3/src/amd/common/ac_gpu_info.c mesa-24.0.5/src/amd/common/ac_gpu_info.c --- mesa-24.0.3/src/amd/common/ac_gpu_info.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/common/ac_gpu_info.c 2024-04-10 20:17:49.000000000 +0000 @@ -1210,6 +1210,11 @@ */ info->has_pops_missed_overlap_bug = info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN; + /* GFX6 hw bug when the IBO addr is 0 which causes invalid clamping (underflow). + * Setting the IB addr to 2 or higher solves this issue. + */ + info->has_null_index_buffer_clamping_bug = info->gfx_level == GFX6; + /* Drawing from 0-sized index buffers causes hangs on gfx10. */ info->has_zero_index_buffer_bug = info->gfx_level == GFX10; diff -Nru mesa-24.0.3/src/amd/common/ac_gpu_info.h mesa-24.0.5/src/amd/common/ac_gpu_info.h --- mesa-24.0.3/src/amd/common/ac_gpu_info.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/common/ac_gpu_info.h 2024-04-10 20:17:49.000000000 +0000 @@ -96,6 +96,7 @@ bool has_small_prim_filter_sample_loc_bug; bool has_ls_vgpr_init_bug; bool has_pops_missed_overlap_bug; + bool has_null_index_buffer_clamping_bug; bool has_zero_index_buffer_bug; bool has_image_load_dcc_bug; bool has_two_planes_iterate256_bug; diff -Nru mesa-24.0.3/src/amd/common/ac_nir_lower_ngg.c mesa-24.0.5/src/amd/common/ac_nir_lower_ngg.c --- mesa-24.0.3/src/amd/common/ac_nir_lower_ngg.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/common/ac_nir_lower_ngg.c 2024-04-10 20:17:49.000000000 +0000 @@ -71,6 +71,7 @@ bool early_prim_export; bool streamout_enabled; bool has_user_edgeflags; + bool skip_primitive_id; unsigned max_num_waves; /* LDS params */ @@ -1760,8 +1761,11 @@ nir_def *addr = pervertex_lds_addr(b, tid, s->pervertex_lds_bytes); u_foreach_bit64(slot, xfb_outputs) { + uint64_t outputs_written = b->shader->info.outputs_written; + if (s->skip_primitive_id) + outputs_written &= ~VARYING_BIT_PRIMITIVE_ID; unsigned packed_location = - util_bitcount64(b->shader->info.outputs_written & BITFIELD64_MASK(slot)); + util_bitcount64(outputs_written & BITFIELD64_MASK(slot)); unsigned mask = xfb_mask[slot]; @@ -1986,7 +1990,8 @@ unsigned stream, nir_def *so_buffer[4], nir_def *buffer_offsets[4], nir_def *vtx_buffer_idx, nir_def *vtx_lds_addr, - shader_output_types *output_types) + shader_output_types *output_types, + bool skip_primitive_id) { nir_def *vtx_buffer_offsets[4]; for (unsigned buffer = 0; buffer < 4; buffer++) { @@ -2009,8 +2014,12 @@ util_bitcount(b->shader->info.outputs_written_16bit & BITFIELD_MASK(out->location - VARYING_SLOT_VAR0_16BIT)); } else { + uint64_t outputs_written = b->shader->info.outputs_written; + if (skip_primitive_id) + outputs_written &= ~VARYING_BIT_PRIMITIVE_ID; + base = - util_bitcount64(b->shader->info.outputs_written & + util_bitcount64(outputs_written & BITFIELD64_MASK(out->location)); } @@ -2099,7 +2108,7 @@ nir_def *vtx_lds_addr = pervertex_lds_addr(b, vtx_lds_idx, vtx_lds_stride); ngg_build_streamout_vertex(b, info, 0, so_buffer, buffer_offsets, nir_iadd_imm(b, vtx_buffer_idx, i), - vtx_lds_addr, &s->output_types); + vtx_lds_addr, &s->output_types, s->skip_primitive_id); } nir_pop_if(b, if_valid_vertex); } @@ -2455,6 +2464,7 @@ .gs_exported_var = gs_exported_var, .max_num_waves = DIV_ROUND_UP(options->max_workgroup_size, options->wave_size), .has_user_edgeflags = has_user_edgeflags, + .skip_primitive_id = streamout_enabled && options->export_primitive_id, }; const bool need_prim_id_store_shared = @@ -3415,7 +3425,7 @@ buffer_offsets, nir_iadd_imm(b, vtx_buffer_idx, i), exported_vtx_lds_addr[i], - &s->output_types); + &s->output_types, false); } } nir_pop_if(b, if_emit); diff -Nru mesa-24.0.3/src/amd/common/ac_surface.h mesa-24.0.5/src/amd/common/ac_surface.h --- mesa-24.0.3/src/amd/common/ac_surface.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/common/ac_surface.h 2024-04-10 20:17:49.000000000 +0000 @@ -76,6 +76,12 @@ #define RADEON_SURF_NO_TEXTURE (1ull << 34) #define RADEON_SURF_NO_STENCIL_ADJUST (1ull << 35) +enum radeon_enc_hevc_surface_alignment +{ + RADEON_ENC_HEVC_SURFACE_LOG2_WIDTH_ALIGNMENT = 6, + RADEON_ENC_HEVC_SURFACE_LOG2_HEIGHT_ALIGNMENT = 4, +}; + struct legacy_surf_level { uint32_t offset_256B; /* divided by 256, the hw can only do 40-bit addresses */ uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */ diff -Nru mesa-24.0.3/src/amd/compiler/aco_assembler.cpp mesa-24.0.5/src/amd/compiler/aco_assembler.cpp --- mesa-24.0.3/src/amd/compiler/aco_assembler.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/compiler/aco_assembler.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -733,10 +733,10 @@ } else if (instr->format != Format::FLAT || ctx.gfx_level >= GFX10) { /* SADDR is actually used with FLAT on GFX10 */ /* For GFX10.3 scratch, 0x7F disables both ADDR and SADDR, unlike sgpr_null, which only - * disables SADDR. + * disables SADDR. On GFX11, this was replaced with SVE. */ if (ctx.gfx_level <= GFX9 || - (instr->format == Format::SCRATCH && instr->operands[0].isUndefined())) + (instr->isScratch() && instr->operands[0].isUndefined() && ctx.gfx_level < GFX11)) encoding |= 0x7F << 16; else encoding |= reg(ctx, sgpr_null) << 16; diff -Nru mesa-24.0.3/src/amd/compiler/aco_instruction_selection.cpp mesa-24.0.5/src/amd/compiler/aco_instruction_selection.cpp --- mesa-24.0.3/src/amd/compiler/aco_instruction_selection.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/compiler/aco_instruction_selection.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -12661,6 +12661,20 @@ program->config->num_sgprs = get_sgpr_alloc(program, num_sgprs); } +PhysReg +get_next_vgpr(unsigned size, unsigned* num, int *offset = NULL) +{ + unsigned reg = *num + (offset ? *offset : 0); + if (reg + size >= *num) { + *num = reg + size; + if (offset) + *offset = 0; + } else if (offset) { + *offset += size; + } + return PhysReg(256 + reg); +} + void select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_shader_config* config, const struct aco_compiler_options* options, const struct aco_shader_info* info, @@ -12702,13 +12716,30 @@ Operand start_instance = get_arg_fixed(args, args->start_instance); Operand instance_id = get_arg_fixed(args, args->instance_id); - PhysReg attributes_start(256 + args->num_vgprs_used); - /* choose vgprs that won't be used for anything else until the last attribute load */ - PhysReg vertex_index(attributes_start.reg() + pinfo->num_attributes * 4 - 1); - PhysReg instance_index(attributes_start.reg() + pinfo->num_attributes * 4 - 2); - PhysReg start_instance_vgpr(attributes_start.reg() + pinfo->num_attributes * 4 - 3); - PhysReg nontrivial_tmp_vgpr0(attributes_start.reg() + pinfo->num_attributes * 4 - 4); - PhysReg nontrivial_tmp_vgpr1(attributes_start.reg() + pinfo->num_attributes * 4); + bool needs_instance_index = + pinfo->instance_rate_inputs & + ~(pinfo->zero_divisors | pinfo->nontrivial_divisors); /* divisor is 1 */ + bool needs_start_instance = pinfo->instance_rate_inputs & pinfo->zero_divisors; + bool needs_vertex_index = ~pinfo->instance_rate_inputs & attrib_mask; + bool needs_tmp_vgpr0 = has_nontrivial_divisors; + bool needs_tmp_vgpr1 = has_nontrivial_divisors && + (program->gfx_level <= GFX8 || program->gfx_level >= GFX11); + + int vgpr_offset = pinfo->misaligned_mask & (1u << (pinfo->num_attributes - 1)) ? 0 : -4; + + unsigned num_vgprs = args->num_vgprs_used; + PhysReg attributes_start = get_next_vgpr(pinfo->num_attributes * 4, &num_vgprs); + PhysReg vertex_index, instance_index, start_instance_vgpr, nontrivial_tmp_vgpr0, nontrivial_tmp_vgpr1; + if (needs_vertex_index) + vertex_index = get_next_vgpr(1, &num_vgprs, &vgpr_offset); + if (needs_instance_index) + instance_index = get_next_vgpr(1, &num_vgprs, &vgpr_offset); + if (needs_start_instance) + start_instance_vgpr = get_next_vgpr(1, &num_vgprs, &vgpr_offset); + if (needs_tmp_vgpr0) + nontrivial_tmp_vgpr0 = get_next_vgpr(1, &num_vgprs, &vgpr_offset); + if (needs_tmp_vgpr1) + nontrivial_tmp_vgpr1 = get_next_vgpr(1, &num_vgprs, &vgpr_offset); bld.sop1(aco_opcode::s_mov_b32, Definition(vertex_buffers, s1), get_arg_fixed(args, args->vertex_buffers)); @@ -12720,16 +12751,10 @@ Operand::c32((unsigned)options->address32_hi)); } - /* calculate vgpr requirements */ - unsigned num_vgprs = attributes_start.reg() - 256; - num_vgprs += pinfo->num_attributes * 4; - if (has_nontrivial_divisors && program->gfx_level <= GFX8) - num_vgprs++; /* make space for nontrivial_tmp_vgpr1 */ - unsigned num_sgprs = 0; - const struct ac_vtx_format_info* vtx_info_table = ac_get_vtx_format_info_table(GFX8, CHIP_POLARIS10); + unsigned num_sgprs = 0; for (unsigned loc = 0; loc < pinfo->num_attributes;) { unsigned num_descs = load_vb_descs(bld, desc, Operand(vertex_buffers, s2), loc, pinfo->num_attributes - loc); @@ -12769,11 +12794,6 @@ } } - bool needs_instance_index = - pinfo->instance_rate_inputs & - ~(pinfo->zero_divisors | pinfo->nontrivial_divisors); /* divisor is 1 */ - bool needs_start_instance = pinfo->instance_rate_inputs & pinfo->zero_divisors; - bool needs_vertex_index = ~pinfo->instance_rate_inputs & attrib_mask; if (needs_vertex_index) bld.vadd32(Definition(vertex_index, v1), get_arg_fixed(args, args->base_vertex), get_arg_fixed(args, args->vertex_id), false, Operand(s2), true); diff -Nru mesa-24.0.3/src/amd/compiler/aco_lower_to_cssa.cpp mesa-24.0.5/src/amd/compiler/aco_lower_to_cssa.cpp --- mesa-24.0.3/src/amd/compiler/aco_lower_to_cssa.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/compiler/aco_lower_to_cssa.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -305,8 +305,11 @@ while (!dom.empty() && !dominates(ctx, dom.back(), current)) dom.pop_back(); /* not the desired parent, remove */ - if (!dom.empty() && interference(ctx, current, dom.back())) + if (!dom.empty() && interference(ctx, current, dom.back())) { + for (Temp t : union_set) + ctx.merge_node_table[t.id()].equal_anc_out = Temp(); return false; /* intersection detected */ + } dom.emplace_back(current); /* otherwise, keep checking */ if (current != dst) diff -Nru mesa-24.0.3/src/amd/compiler/aco_optimizer.cpp mesa-24.0.5/src/amd/compiler/aco_optimizer.cpp --- mesa-24.0.3/src/amd/compiler/aco_optimizer.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/compiler/aco_optimizer.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -3851,6 +3851,8 @@ bool fadd = instr->opcode == aco_opcode::v_pk_add_f16; if (fadd && instr->definitions[0].isPrecise()) return; + if (!fadd && instr->valu().clamp) + return; Instruction* mul_instr = nullptr; unsigned add_op_idx = 0; @@ -4506,20 +4508,20 @@ } } else if (instr->opcode == aco_opcode::v_not_b32 && ctx.program->gfx_level >= GFX10) { combine_not_xor(ctx, instr); - } else if (instr->opcode == aco_opcode::v_add_u16) { + } else if (instr->opcode == aco_opcode::v_add_u16 && !instr->valu().clamp) { combine_three_valu_op( ctx, instr, aco_opcode::v_mul_lo_u16, ctx.program->gfx_level == GFX8 ? aco_opcode::v_mad_legacy_u16 : aco_opcode::v_mad_u16, "120", 1 | 2); - } else if (instr->opcode == aco_opcode::v_add_u16_e64) { + } else if (instr->opcode == aco_opcode::v_add_u16_e64 && !instr->valu().clamp) { combine_three_valu_op(ctx, instr, aco_opcode::v_mul_lo_u16_e64, aco_opcode::v_mad_u16, "120", 1 | 2); - } else if (instr->opcode == aco_opcode::v_add_u32) { + } else if (instr->opcode == aco_opcode::v_add_u32 && !instr->usesModifiers()) { if (combine_add_sub_b2i(ctx, instr, aco_opcode::v_addc_co_u32, 1 | 2)) { } else if (combine_add_bcnt(ctx, instr)) { } else if (combine_three_valu_op(ctx, instr, aco_opcode::v_mul_u32_u24, aco_opcode::v_mad_u32_u24, "120", 1 | 2)) { - } else if (ctx.program->gfx_level >= GFX9 && !instr->usesModifiers()) { + } else if (ctx.program->gfx_level >= GFX9) { if (combine_three_valu_op(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::v_xad_u32, "120", 1 | 2)) { } else if (combine_three_valu_op(ctx, instr, aco_opcode::v_xor_b32, aco_opcode::v_xad_u32, @@ -4533,8 +4535,9 @@ } else if (combine_add_or_then_and_lshl(ctx, instr)) { } } - } else if (instr->opcode == aco_opcode::v_add_co_u32 || - instr->opcode == aco_opcode::v_add_co_u32_e64) { + } else if ((instr->opcode == aco_opcode::v_add_co_u32 || + instr->opcode == aco_opcode::v_add_co_u32_e64) && + !instr->usesModifiers()) { bool carry_out = ctx.uses[instr->definitions[1].tempId()] > 0; if (combine_add_sub_b2i(ctx, instr, aco_opcode::v_addc_co_u32, 1 | 2)) { } else if (!carry_out && combine_add_bcnt(ctx, instr)) { diff -Nru mesa-24.0.3/src/amd/compiler/aco_register_allocation.cpp mesa-24.0.5/src/amd/compiler/aco_register_allocation.cpp --- mesa-24.0.3/src/amd/compiler/aco_register_allocation.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/compiler/aco_register_allocation.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -47,7 +47,8 @@ RegClass rc); std::pair get_subdword_definition_info(Program* program, const aco_ptr& instr, RegClass rc); -void add_subdword_definition(Program* program, aco_ptr& instr, PhysReg reg); +void add_subdword_definition(Program* program, aco_ptr& instr, PhysReg reg, + bool allow_16bit_write); struct assignment { PhysReg reg; @@ -678,7 +679,8 @@ } void -add_subdword_definition(Program* program, aco_ptr& instr, PhysReg reg) +add_subdword_definition(Program* program, aco_ptr& instr, PhysReg reg, + bool allow_16bit_write) { if (instr->isPseudo()) return; @@ -687,7 +689,7 @@ amd_gfx_level gfx_level = program->gfx_level; assert(instr->definitions[0].bytes() <= 2); - if (reg.byte() == 0 && instr_is_16bit(gfx_level, instr->opcode)) + if (reg.byte() == 0 && allow_16bit_write && instr_is_16bit(gfx_level, instr->opcode)) return; /* use SDWA */ @@ -696,6 +698,8 @@ return; } + assert(allow_16bit_write); + if (instr->opcode == aco_opcode::v_fma_mixlo_f16) { instr->opcode = aco_opcode::v_fma_mixhi_f16; return; @@ -2979,7 +2983,8 @@ PhysReg reg = get_reg(ctx, register_file, tmp, parallelcopy, instr); definition->setFixed(reg); if (reg.byte() || register_file.test(reg, 4)) { - add_subdword_definition(program, instr, reg); + bool allow_16bit_write = reg.byte() % 2 == 0 && !register_file.test(reg, 2); + add_subdword_definition(program, instr, reg, allow_16bit_write); definition = &instr->definitions[i]; /* add_subdword_definition can invalidate the reference */ } diff -Nru mesa-24.0.3/src/amd/compiler/tests/test_assembler.cpp mesa-24.0.5/src/amd/compiler/tests/test_assembler.cpp --- mesa-24.0.3/src/amd/compiler/tests/test_assembler.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/compiler/tests/test_assembler.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -741,6 +741,9 @@ //! scratch_load_b32 v42, v10, s32 ; dc510000 2aa0000a bld.scratch(aco_opcode::scratch_load_dword, dst_v1, op_v1, op_s1); + //! scratch_load_b32 v42, off, off ; dc510000 2a7c0080 + bld.scratch(aco_opcode::scratch_load_dword, dst_v1, Operand(v1), Operand(s1)); + //! global_load_b32 v42, v[20:21], off offset:-42 ; dc521fd6 2a7c0014 bld.global(aco_opcode::global_load_dword, dst_v1, op_v2, Operand(s1), -42); diff -Nru mesa-24.0.3/src/amd/llvm/ac_llvm_build.c mesa-24.0.5/src/amd/llvm/ac_llvm_build.c --- mesa-24.0.3/src/amd/llvm/ac_llvm_build.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/llvm/ac_llvm_build.c 2024-04-10 20:17:49.000000000 +0000 @@ -119,6 +119,8 @@ free(ctx->flow->stack); free(ctx->flow); ctx->flow = NULL; + + LLVMDisposeBuilder(ctx->builder); } int ac_get_llvm_num_components(LLVMValueRef value) diff -Nru mesa-24.0.3/src/amd/llvm/ac_nir_to_llvm.c mesa-24.0.5/src/amd/llvm/ac_nir_to_llvm.c --- mesa-24.0.3/src/amd/llvm/ac_nir_to_llvm.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/llvm/ac_nir_to_llvm.c 2024-04-10 20:17:49.000000000 +0000 @@ -1935,7 +1935,6 @@ LLVMValueRef offset = get_src(ctx, instr->src[1]); LLVMValueRef rsrc = ctx->abi->load_ssbo ? ctx->abi->load_ssbo(ctx->abi, rsrc_base, false, false) : rsrc_base; - LLVMValueRef vindex = ctx->ac.i32_0; LLVMTypeRef def_type = get_def_type(ctx, &instr->def); LLVMTypeRef def_elem_type = num_components > 1 ? LLVMGetElementType(def_type) : def_type; @@ -1964,7 +1963,7 @@ int num_channels = util_next_power_of_two(load_bytes) / 4; bool can_speculate = access & ACCESS_CAN_REORDER; - ret = ac_build_buffer_load(&ctx->ac, rsrc, num_channels, vindex, voffset, ctx->ac.i32_0, + ret = ac_build_buffer_load(&ctx->ac, rsrc, num_channels, NULL, voffset, ctx->ac.i32_0, ctx->ac.f32, access, can_speculate, false); } @@ -4366,6 +4365,7 @@ { struct ac_nir_context ctx = {0}; struct nir_function *func; + bool ret; ctx.ac = *ac; ctx.abi = abi; @@ -4395,10 +4395,8 @@ if (gl_shader_stage_is_compute(nir->info.stage)) setup_shared(&ctx, nir); - if (!visit_cf_list(&ctx, &func->impl->body)) - return false; - - phi_post_pass(&ctx); + if ((ret = visit_cf_list(&ctx, &func->impl->body))) + phi_post_pass(&ctx); free(ctx.ssa_defs); ralloc_free(ctx.defs); @@ -4406,7 +4404,7 @@ if (ctx.abi->kill_ps_if_inf_interp) ralloc_free(ctx.verified_interp); - return true; + return ret; } /* Fixup the HW not emitting the TCS regs if there are no HS threads. */ diff -Nru mesa-24.0.3/src/amd/registers/gfx11.json mesa-24.0.5/src/amd/registers/gfx11.json --- mesa-24.0.3/src/amd/registers/gfx11.json 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/registers/gfx11.json 2024-04-10 20:17:49.000000000 +0000 @@ -20,8 +20,8 @@ "entries": [ {"name": "BINNING_ALLOWED", "value": 0}, {"name": "FORCE_BINNING_ON", "value": 1}, - {"name": "DISABLE_BINNING_USE_NEW_SC", "value": 2}, - {"name": "DISABLE_BINNING_USE_LEGACY_SC", "value": 3} + {"name": "BINNING_ONE_PRIM_PER_BATCH", "value": 2}, + {"name": "BINNING_DISABLED", "value": 3} ] }, "BlendOp": { diff -Nru mesa-24.0.3/src/amd/registers/gfx115.json mesa-24.0.5/src/amd/registers/gfx115.json --- mesa-24.0.3/src/amd/registers/gfx115.json 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/registers/gfx115.json 2024-04-10 20:17:49.000000000 +0000 @@ -20,8 +20,7 @@ "entries": [ {"name": "BINNING_ALLOWED", "value": 0}, {"name": "FORCE_BINNING_ON", "value": 1}, - {"name": "DISABLE_BINNING_USE_NEW_SC", "value": 2}, - {"name": "DISABLE_BINNING_USE_LEGACY_SC", "value": 3} + {"name": "BINNING_DISABLED", "value": 3} ] }, "BlendOp": { diff -Nru mesa-24.0.3/src/amd/registers/parse_kernel_headers.py mesa-24.0.5/src/amd/registers/parse_kernel_headers.py --- mesa-24.0.3/src/amd/registers/parse_kernel_headers.py 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/registers/parse_kernel_headers.py 2024-04-10 20:17:49.000000000 +0000 @@ -444,6 +444,23 @@ ] } +BinningModeGfx11 = { + "entries": [ + {"name": "BINNING_ALLOWED", "value": 0}, + {"name": "FORCE_BINNING_ON", "value": 1}, + {"name": "BINNING_ONE_PRIM_PER_BATCH", "value": 2}, + {"name": "BINNING_DISABLED", "value": 3} + ] +} + +BinningModeGfx115Plus = { + "entries": [ + {"name": "BINNING_ALLOWED", "value": 0}, + {"name": "FORCE_BINNING_ON", "value": 1}, + {"name": "BINNING_DISABLED", "value": 3} + ] +} + missing_enums_all = { 'FLOAT_MODE': { "entries": [ @@ -669,6 +686,11 @@ }, } +missing_enums_gfx115plus = { + **missing_enums_gfx11plus, + "BinningMode": BinningModeGfx115Plus, +} + enums_missing = { 'gfx6': { **missing_enums_all, @@ -704,9 +726,10 @@ }, 'gfx11': { **missing_enums_gfx11plus, + "BinningMode": BinningModeGfx11, }, 'gfx115': { - **missing_enums_gfx11plus, + **missing_enums_gfx115plus, }, } diff -Nru mesa-24.0.3/src/amd/vulkan/radv_cmd_buffer.c mesa-24.0.5/src/amd/vulkan/radv_cmd_buffer.c --- mesa-24.0.3/src/amd/vulkan/radv_cmd_buffer.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/vulkan/radv_cmd_buffer.c 2024-04-10 20:17:49.000000000 +0000 @@ -1551,6 +1551,8 @@ uint32_t pa_sc_binner_cntl_0; if (pdevice->rad_info.gfx_level >= GFX10) { + const unsigned binning_disabled = + pdevice->rad_info.gfx_level >= GFX11_5 ? V_028C44_BINNING_DISABLED : V_028C44_DISABLE_BINNING_USE_NEW_SC; unsigned min_bytes_per_pixel = 0; for (unsigned i = 0; i < render->color_att_count; ++i) { @@ -1567,8 +1569,8 @@ min_bytes_per_pixel = bytes; } - pa_sc_binner_cntl_0 = S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) | S_028C44_BIN_SIZE_X(0) | - S_028C44_BIN_SIZE_Y(0) | S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */ + pa_sc_binner_cntl_0 = S_028C44_BINNING_MODE(binning_disabled) | S_028C44_BIN_SIZE_X(0) | S_028C44_BIN_SIZE_Y(0) | + S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */ S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */ S_028C44_DISABLE_START_OF_PRIM(1) | S_028C44_FLUSH_ON_BINNING_TRANSITION(1); } else { @@ -3743,7 +3745,8 @@ if (!enable_occlusion_queries) { db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(gfx_level < GFX11); } else { - uint32_t sample_rate = util_logbase2(cmd_buffer->state.render.max_samples); + const uint32_t rasterization_samples = radv_get_rasterization_samples(cmd_buffer); + const uint32_t sample_rate = util_logbase2(rasterization_samples); bool gfx10_perfect = gfx_level >= GFX10 && (cmd_buffer->state.perfect_occlusion_queries_enabled || cmd_buffer->state.inherited_query_control_flags & VK_QUERY_CONTROL_PRECISE_BIT); @@ -5609,6 +5612,9 @@ flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; break; case VK_ACCESS_2_MEMORY_READ_BIT: + if (has_CB_meta || has_DB_meta) + flush_bits |= RADV_CMD_FLAG_INV_L2_METADATA; + FALLTHROUGH; case VK_ACCESS_2_MEMORY_WRITE_BIT: flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE; if (!image_is_coherent) @@ -5955,6 +5961,9 @@ } else { cmd_buffer->state.index_va = 0; cmd_buffer->state.max_index_count = 0; + + if (cmd_buffer->device->physical_device->rad_info.has_null_index_buffer_clamping_bug) + cmd_buffer->state.index_va = 0x2; } cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER; @@ -8571,10 +8580,7 @@ { const uint32_t view_mask = cmd_buffer->state.render.view_mask; const unsigned num_views = MAX2(1, util_bitcount(view_mask)); - unsigned ace_predication_size = num_views * 6; /* DISPATCH_TASKMESH_DIRECT_ACE size */ - - if (num_views > 1) - ace_predication_size += num_views * 3; /* SET_SH_REG size (view index SGPR) */ + const unsigned ace_predication_size = num_views * 6; /* DISPATCH_TASKMESH_DIRECT_ACE size */ radv_emit_userdata_task(cmd_buffer, x, y, z, 0); radv_cs_emit_compute_predication(cmd_buffer->device, &cmd_buffer->state, cmd_buffer->gang.cs, @@ -8608,9 +8614,6 @@ info->count_buffer->offset + info->count_buffer_offset; uint64_t workaround_cond_va = 0; - if (num_views > 1) - ace_predication_size += num_views * 3; /* SET_SH_REG size (view index SGPR) */ - if (count_va) radv_cs_add_buffer(ws, cmd_buffer->gang.cs, info->count_buffer->bo); @@ -9006,7 +9009,8 @@ if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_SHADER_QUERY) radv_flush_shader_query_state(cmd_buffer); - if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_OCCLUSION_QUERY) + if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_OCCLUSION_QUERY | RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES | + RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) radv_flush_occlusion_query_state(cmd_buffer); if ((cmd_buffer->state.dirty & diff -Nru mesa-24.0.3/src/amd/vulkan/radv_device.c mesa-24.0.5/src/amd/vulkan/radv_device.c --- mesa-24.0.3/src/amd/vulkan/radv_device.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/vulkan/radv_device.c 2024-04-10 20:17:49.000000000 +0000 @@ -1248,6 +1248,12 @@ device->capture_replay_arena_vas = _mesa_hash_table_u64_create(NULL); } + if (device->physical_device->rad_info.gfx_level == GFX11 && device->physical_device->rad_info.has_dedicated_vram && + device->instance->drirc.force_pstate_peak_gfx11_dgpu) { + if (!radv_device_acquire_performance_counters(device)) + fprintf(stderr, "radv: failed to set pstate to profile_peak.\n"); + } + *pDevice = radv_device_to_handle(device); return VK_SUCCESS; diff -Nru mesa-24.0.3/src/amd/vulkan/radv_instance.c mesa-24.0.5/src/amd/vulkan/radv_instance.c --- mesa-24.0.3/src/amd/vulkan/radv_instance.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/vulkan/radv_instance.c 2024-04-10 20:17:49.000000000 +0000 @@ -155,6 +155,7 @@ DRI_CONF_RADV_FLUSH_BEFORE_TIMESTAMP_WRITE(false) DRI_CONF_RADV_RT_WAVE64(false) DRI_CONF_RADV_LEGACY_SPARSE_BINDING(false) + DRI_CONF_RADV_FORCE_PSTATE_PEAK_GFX11_DGPU(false) DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION(false) DRI_CONF_RADV_OVERRIDE_GRAPHICS_SHADER_VERSION(0) DRI_CONF_RADV_OVERRIDE_COMPUTE_SHADER_VERSION(0) @@ -231,6 +232,9 @@ instance->drirc.legacy_sparse_binding = driQueryOptionb(&instance->drirc.options, "radv_legacy_sparse_binding"); + instance->drirc.force_pstate_peak_gfx11_dgpu = + driQueryOptionb(&instance->drirc.options, "radv_force_pstate_peak_gfx11_dgpu"); + instance->drirc.override_graphics_shader_version = driQueryOptioni(&instance->drirc.options, "radv_override_graphics_shader_version"); instance->drirc.override_compute_shader_version = diff -Nru mesa-24.0.3/src/amd/vulkan/radv_nir_to_llvm.c mesa-24.0.5/src/amd/vulkan/radv_nir_to_llvm.c --- mesa-24.0.3/src/amd/vulkan/radv_nir_to_llvm.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/vulkan/radv_nir_to_llvm.c 2024-04-10 20:17:49.000000000 +0000 @@ -262,7 +262,6 @@ ac_llvm_finalize_module(struct radv_shader_context *ctx, LLVMPassManagerRef passmgr) { LLVMRunPassManager(passmgr, ctx->ac.module); - LLVMDisposeBuilder(ctx->ac.builder); ac_llvm_context_dispose(&ctx->ac); } diff -Nru mesa-24.0.3/src/amd/vulkan/radv_physical_device.c mesa-24.0.5/src/amd/vulkan/radv_physical_device.c --- mesa-24.0.3/src/amd/vulkan/radv_physical_device.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/vulkan/radv_physical_device.c 2024-04-10 20:17:49.000000000 +0000 @@ -2380,6 +2380,11 @@ assert(heap == memory_properties->memoryHeapCount); } + /* The heapBudget value must be less than or equal to VkMemoryHeap::size for each heap. */ + for (uint32_t i = 0; i < memory_properties->memoryHeapCount; i++) { + memoryBudget->heapBudget[i] = MIN2(memory_properties->memoryHeaps[i].size, memoryBudget->heapBudget[i]); + } + /* The heapBudget and heapUsage values must be zero for array elements * greater than or equal to * VkPhysicalDeviceMemoryProperties::memoryHeapCount. diff -Nru mesa-24.0.3/src/amd/vulkan/radv_private.h mesa-24.0.5/src/amd/vulkan/radv_private.h --- mesa-24.0.3/src/amd/vulkan/radv_private.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/vulkan/radv_private.h 2024-04-10 20:17:49.000000000 +0000 @@ -380,6 +380,7 @@ bool force_rt_wave64; bool dual_color_blend_by_location; bool legacy_sparse_binding; + bool force_pstate_peak_gfx11_dgpu; bool clear_lds; bool enable_dgc; bool enable_khr_present_wait; diff -Nru mesa-24.0.3/src/amd/vulkan/radv_video.c mesa-24.0.5/src/amd/vulkan/radv_video.c --- mesa-24.0.3/src/amd/vulkan/radv_video.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/vulkan/radv_video.c 2024-04-10 20:17:49.000000000 +0000 @@ -39,8 +39,7 @@ #include "radv_cs.h" #include "radv_debug.h" -#define NUM_H264_REFS 17 -#define NUM_H265_REFS 8 +#define NUM_H2645_REFS 16 #define FB_BUFFER_OFFSET 0x1000 #define FB_BUFFER_SIZE 2048 #define FB_BUFFER_SIZE_TONGA (2048 * 64) @@ -444,8 +443,8 @@ if (pVideoProfile->lumaBitDepth != VK_VIDEO_COMPONENT_BIT_DEPTH_8_BIT_KHR) return VK_ERROR_VIDEO_PROFILE_FORMAT_NOT_SUPPORTED_KHR; - pCapabilities->maxDpbSlots = NUM_H264_REFS; - pCapabilities->maxActiveReferencePictures = NUM_H264_REFS; + pCapabilities->maxDpbSlots = NUM_H2645_REFS + 1; + pCapabilities->maxActiveReferencePictures = NUM_H2645_REFS; /* for h264 on navi21+ separate dpb images should work */ if (radv_enable_tier2(pdevice)) @@ -473,8 +472,8 @@ pVideoProfile->lumaBitDepth != VK_VIDEO_COMPONENT_BIT_DEPTH_10_BIT_KHR) return VK_ERROR_VIDEO_PROFILE_FORMAT_NOT_SUPPORTED_KHR; - pCapabilities->maxDpbSlots = NUM_H264_REFS; - pCapabilities->maxActiveReferencePictures = NUM_H265_REFS; + pCapabilities->maxDpbSlots = NUM_H2645_REFS + 1; + pCapabilities->maxActiveReferencePictures = NUM_H2645_REFS; /* for h265 on navi21+ separate dpb images should work */ if (radv_enable_tier2(pdevice)) pCapabilities->flags |= VK_VIDEO_CAPABILITY_SEPARATE_REFERENCE_IMAGES_BIT_KHR; @@ -935,7 +934,10 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct radv_device *device, struct radv_video_session *vid, struct radv_video_session_params *params, - const struct VkVideoDecodeInfoKHR *frame_info, void *it_ptr) + const struct VkVideoDecodeInfoKHR *frame_info, + uint32_t *width_in_samples, + uint32_t *height_in_samples, + void *it_ptr) { rvcn_dec_message_hevc_t result; int i, j; @@ -967,6 +969,8 @@ } result.st_rps_bits = h265_pic_info->pStdPictureInfo->NumBitsForSTRefPicSetInSlice; + *width_in_samples = sps->pic_width_in_luma_samples; + *height_in_samples = sps->pic_height_in_luma_samples; result.chroma_format = sps->chroma_format_idc; result.bit_depth_luma_minus8 = sps->bit_depth_luma_minus8; result.bit_depth_chroma_minus8 = sps->bit_depth_chroma_minus8; @@ -1221,7 +1225,8 @@ break; } case VK_VIDEO_CODEC_OPERATION_DECODE_H265_BIT_KHR: { - rvcn_dec_message_hevc_t hevc = get_h265_msg(device, vid, params, frame_info, it_ptr); + rvcn_dec_message_hevc_t hevc = + get_h265_msg(device, vid, params, frame_info, &decode->width_in_samples, &decode->height_in_samples, it_ptr); memcpy(codec, (void *)&hevc, sizeof(rvcn_dec_message_hevc_t)); index_codec->message_id = RDECODE_MESSAGE_HEVC; break; @@ -1378,7 +1383,8 @@ static struct ruvd_h265 get_uvd_h265_msg(struct radv_device *device, struct radv_video_session *vid, struct radv_video_session_params *params, - const struct VkVideoDecodeInfoKHR *frame_info, void *it_ptr) + const struct VkVideoDecodeInfoKHR *frame_info, uint32_t *width_in_samples, + uint32_t *height_in_samples, void *it_ptr) { struct ruvd_h265 result; int i, j; @@ -1406,6 +1412,8 @@ if (device->physical_device->rad_info.family == CHIP_CARRIZO) result.sps_info_flags |= 1 << 9; + *width_in_samples = sps->pic_width_in_luma_samples; + *height_in_samples = sps->pic_height_in_luma_samples; result.chroma_format = sps->chroma_format_idc; result.bit_depth_luma_minus8 = sps->bit_depth_luma_minus8; result.bit_depth_chroma_minus8 = sps->bit_depth_chroma_minus8; @@ -1579,7 +1587,10 @@ break; } case VK_VIDEO_CODEC_OPERATION_DECODE_H265_BIT_KHR: { - msg->body.decode.codec.h265 = get_uvd_h265_msg(device, vid, params, frame_info, it_ptr); + msg->body.decode.codec.h265 = get_uvd_h265_msg(device, vid, params, frame_info, + &msg->body.decode.width_in_samples, + &msg->body.decode.height_in_samples, + it_ptr); if (vid->ctx.mem) msg->body.decode.dpb_reserved = vid->ctx.size; diff -Nru mesa-24.0.3/src/amd/vulkan/si_cmd_buffer.c mesa-24.0.5/src/amd/vulkan/si_cmd_buffer.c --- mesa-24.0.3/src/amd/vulkan/si_cmd_buffer.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/amd/vulkan/si_cmd_buffer.c 2024-04-10 20:17:49.000000000 +0000 @@ -84,14 +84,18 @@ radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1, * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */ - radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); - radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); + for (unsigned i = 0; i < 2; ++i) { + unsigned cu_mask = i < info->num_se ? info->spi_cu_en : 0x0; + radeon_emit(cs, S_00B8AC_SA0_CU_EN(cu_mask) | S_00B8AC_SA1_CU_EN(cu_mask)); + } if (device->physical_device->rad_info.gfx_level >= GFX7) { /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */ radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2); - radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); - radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); + for (unsigned i = 2; i < 4; ++i) { + unsigned cu_mask = i < info->num_se ? info->spi_cu_en : 0x0; + radeon_emit(cs, S_00B8AC_SA0_CU_EN(cu_mask) | S_00B8AC_SA1_CU_EN(cu_mask)); + } if (device->border_color_data.bo) { uint64_t bc_va = radv_buffer_get_va(device->border_color_data.bo); @@ -140,13 +144,12 @@ } if (device->physical_device->rad_info.gfx_level >= GFX11) { - uint32_t spi_cu_en = device->physical_device->rad_info.spi_cu_en; - radeon_set_sh_reg_seq(cs, R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4, 4); - radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE4 */ - radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE5 */ - radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE6 */ - radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE7 */ + /* SE4-SE7 */ + for (unsigned i = 4; i < 8; ++i) { + unsigned cu_mask = i < info->num_se ? info->spi_cu_en : 0x0; + radeon_emit(cs, S_00B8AC_SA0_CU_EN(cu_mask) | S_00B8AC_SA1_CU_EN(cu_mask)); + } radeon_set_sh_reg(cs, R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE, 64); } @@ -511,9 +514,14 @@ } if (physical_device->rad_info.gfx_level >= GFX9) { + unsigned max_alloc_count = physical_device->rad_info.pbb_max_alloc_count; + + /* GFX11+ shouldn't subtract 1 from pbb_max_alloc_count. */ + if (physical_device->rad_info.gfx_level < GFX11) + max_alloc_count -= 1; + radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1, - S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) | - S_028C48_MAX_PRIM_PER_BATCH(1023)); + S_028C48_MAX_ALLOC_COUNT(max_alloc_count) | S_028C48_MAX_PRIM_PER_BATCH(1023)); radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1)); radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0); } diff -Nru mesa-24.0.3/src/broadcom/compiler/nir_to_vir.c mesa-24.0.5/src/broadcom/compiler/nir_to_vir.c --- mesa-24.0.3/src/broadcom/compiler/nir_to_vir.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/broadcom/compiler/nir_to_vir.c 2024-04-10 20:17:49.000000000 +0000 @@ -2745,8 +2745,21 @@ SYSTEM_VALUE_VERTEX_ID)) { index++; } - for (int i = 0; i < offset; i++) - index += c->vattr_sizes[i]; + + for (int i = 0; i < offset; i++) { + /* GFXH-1602: if any builtins (vid, iid, etc) are read then + * attribute 0 must be active (size > 0). When we hit this, + * the driver is expected to program attribute 0 to have a + * size of 1, so here we need to add that. + */ + if (i == 0 && c->vs_key->is_coord && + c->vattr_sizes[i] == 0 && index > 0) { + index++; + } else { + index += c->vattr_sizes[i]; + } + } + index += nir_intrinsic_component(instr); for (int i = 0; i < instr->num_components; i++) { struct qreg vpm_offset = vir_uniform_ui(c, index++); diff -Nru mesa-24.0.3/src/compiler/glsl/ast_to_hir.cpp mesa-24.0.5/src/compiler/glsl/ast_to_hir.cpp --- mesa-24.0.3/src/compiler/glsl/ast_to_hir.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/compiler/glsl/ast_to_hir.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -6058,7 +6058,7 @@ */ if ((var->data.mode == ir_var_function_inout || var->data.mode == ir_var_function_out) && glsl_type_is_array(type) - && !state->check_version(120, 100, &loc, + && !state->check_version(state->allow_glsl_120_subset_in_110 ? 110 : 120, 100, &loc, "arrays cannot be out or inout parameters")) { type = &glsl_type_builtin_error; } diff -Nru mesa-24.0.3/src/compiler/glsl/gl_nir_link_varyings.c mesa-24.0.5/src/compiler/glsl/gl_nir_link_varyings.c --- mesa-24.0.3/src/compiler/glsl/gl_nir_link_varyings.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/compiler/glsl/gl_nir_link_varyings.c 2024-04-10 20:17:49.000000000 +0000 @@ -50,6 +50,7 @@ /* Temporary storage for the set of attributes that need locations assigned. */ struct temp_attr { unsigned slots; + unsigned original_idx; nir_variable *var; }; @@ -61,7 +62,10 @@ const struct temp_attr *const r = (const struct temp_attr *) b; /* Reversed because we want a descending order sort below. */ - return r->slots - l->slots; + if (r->slots != l->slots) + return r->slots - l->slots; + + return l->original_idx - r->original_idx; } /** @@ -1238,6 +1242,7 @@ } to_assign[num_attr].slots = slots; to_assign[num_attr].var = var; + to_assign[num_attr].original_idx = num_attr; num_attr++; } diff -Nru mesa-24.0.3/src/compiler/glsl/gl_nir_linker.c mesa-24.0.5/src/compiler/glsl/gl_nir_linker.c --- mesa-24.0.3/src/compiler/glsl/gl_nir_linker.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/compiler/glsl/gl_nir_linker.c 2024-04-10 20:17:49.000000000 +0000 @@ -921,6 +921,8 @@ nir_deref_instr *deref = nir_build_deref_var(&b, psiz); nir_store_deref(&b, deref, nir_imm_float(&b, 1.0), BITFIELD_BIT(0)); } + + nir->info.outputs_written |= VARYING_BIT_PSIZ; } static void @@ -1162,6 +1164,8 @@ if (!prelink_lowering(consts, exts, prog, linked_shader, num_shaders)) return false; + gl_nir_link_assign_xfb_resources(consts, prog); + /* Linking the stages in the opposite order (from fragment to vertex) * ensures that inter-shader outputs written to in an earlier stage * are eliminated if they are (transitively) not used in a later @@ -1191,7 +1195,6 @@ return false; gl_nir_link_assign_atomic_counter_resources(consts, prog); - gl_nir_link_assign_xfb_resources(consts, prog); return true; } diff -Nru mesa-24.0.3/src/compiler/glsl_types.c mesa-24.0.5/src/compiler/glsl_types.c --- mesa-24.0.3/src/compiler/glsl_types.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/compiler/glsl_types.c 2024-04-10 20:17:49.000000000 +0000 @@ -3145,6 +3145,11 @@ encode_type_to_blob(blob, type->fields.array); return; case GLSL_TYPE_COOPERATIVE_MATRIX: + /* The first 5 bits of encoded/decoded are used to identify the + * actual type, but cmat_desc already is 32-bit without that tag, so + * encode just the cmat base type first, then the actual cmat desc. + */ + blob_write_uint32(blob, encoded.u32); encoded.cmat_desc = type->cmat_desc; blob_write_uint32(blob, encoded.u32); return; @@ -3255,6 +3260,7 @@ explicit_stride); } case GLSL_TYPE_COOPERATIVE_MATRIX: { + encoded.u32 = blob_read_uint32(blob); return glsl_cmat_type(&encoded.cmat_desc); } case GLSL_TYPE_STRUCT: diff -Nru mesa-24.0.3/src/compiler/nir/nir_builder.c mesa-24.0.5/src/compiler/nir/nir_builder.c --- mesa-24.0.3/src/compiler/nir/nir_builder.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/compiler/nir/nir_builder.c 2024-04-10 20:17:49.000000000 +0000 @@ -380,6 +380,22 @@ } void +nir_builder_instr_insert_at_top(nir_builder *build, nir_instr *instr) +{ + nir_cursor top = nir_before_impl(build->impl); + const bool at_top = build->cursor.block != NULL && + nir_cursors_equal(build->cursor, top); + + nir_instr_insert(top, instr); + + if (build->update_divergence) + nir_update_instr_divergence(build->shader, instr); + + if (at_top) + build->cursor = nir_after_instr(instr); +} + +void nir_builder_cf_insert(nir_builder *build, nir_cf_node *cf) { nir_cf_node_insert(build->cursor, cf); diff -Nru mesa-24.0.3/src/compiler/nir/nir_builder.h mesa-24.0.5/src/compiler/nir/nir_builder.h --- mesa-24.0.3/src/compiler/nir/nir_builder.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/compiler/nir/nir_builder.h 2024-04-10 20:17:49.000000000 +0000 @@ -182,6 +182,7 @@ } void nir_builder_instr_insert(nir_builder *build, nir_instr *instr); +void nir_builder_instr_insert_at_top(nir_builder *build, nir_instr *instr); static inline nir_instr * nir_builder_last_instr(nir_builder *build) @@ -250,9 +251,7 @@ if (!undef) return NULL; - nir_instr_insert(nir_before_impl(build->impl), &undef->instr); - if (build->update_divergence) - nir_update_instr_divergence(build->shader, &undef->instr); + nir_builder_instr_insert_at_top(build, &undef->instr); return &undef->def; } @@ -1832,7 +1831,7 @@ nir_intrinsic_set_divergent(decl, true); nir_def_init(&decl->instr, &decl->def, 1, 32); - nir_instr_insert(nir_before_impl(b->impl), &decl->instr); + nir_builder_instr_insert_at_top(b, &decl->instr); return &decl->def; } diff -Nru mesa-24.0.3/src/compiler/nir/nir_gather_types.c mesa-24.0.5/src/compiler/nir/nir_gather_types.c --- mesa-24.0.3/src/compiler/nir/nir_gather_types.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/compiler/nir/nir_gather_types.c 2024-04-10 20:17:49.000000000 +0000 @@ -103,7 +103,7 @@ do { progress = false; - nir_foreach_block(block, impl) { + nir_foreach_block_unstructured(block, impl) { nir_foreach_instr(instr, block) { switch (instr->type) { case nir_instr_type_alu: { diff -Nru mesa-24.0.3/src/compiler/nir/nir_intrinsics.py mesa-24.0.5/src/compiler/nir/nir_intrinsics.py --- mesa-24.0.3/src/compiler/nir/nir_intrinsics.py 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/compiler/nir/nir_intrinsics.py 2024-04-10 20:17:49.000000000 +0000 @@ -2025,11 +2025,15 @@ system_value("btd_shader_type_intel", 1) system_value("ray_query_global_intel", 1, bit_sizes=[64]) -# Source 0: A matrix (type specified by SRC_TYPE) -# Source 1: B matrix (type specified by SRC_TYPE) -# Source 2: Accumulator matrix (type specified by DEST_TYPE) +# Source 0: Accumulator matrix (type specified by DEST_TYPE) +# Source 1: A matrix (type specified by SRC_TYPE) +# Source 2: B matrix (type specified by SRC_TYPE) # # The matrix parameters are the slices owned by the invocation. +# +# The accumulator is source 0 because that is the source the intrinsic +# infrastructure in NIR uses to determine the number of components in the +# result. intrinsic("dpas_intel", dest_comp=0, src_comp=[0, 0, 0], indices=[DEST_TYPE, SRC_TYPE, SATURATE, CMAT_SIGNED_MASK, SYSTOLIC_DEPTH, REPEAT_COUNT], flags=[CAN_ELIMINATE]) diff -Nru mesa-24.0.3/src/compiler/nir/nir_lower_clamp_color_outputs.c mesa-24.0.5/src/compiler/nir/nir_lower_clamp_color_outputs.c --- mesa-24.0.3/src/compiler/nir/nir_lower_clamp_color_outputs.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/compiler/nir/nir_lower_clamp_color_outputs.c 2024-04-10 20:17:49.000000000 +0000 @@ -25,13 +25,13 @@ #include "nir_builder.h" static bool -is_color_output(nir_shader *shader, nir_variable *out) +is_color_output(nir_shader *shader, int location) { switch (shader->info.stage) { case MESA_SHADER_VERTEX: case MESA_SHADER_GEOMETRY: case MESA_SHADER_TESS_EVAL: - switch (out->data.location) { + switch (location) { case VARYING_SLOT_COL0: case VARYING_SLOT_COL1: case VARYING_SLOT_BFC0: @@ -42,8 +42,8 @@ } break; case MESA_SHADER_FRAGMENT: - return (out->data.location == FRAG_RESULT_COLOR || - out->data.location >= FRAG_RESULT_DATA0); + return (location == FRAG_RESULT_COLOR || + location >= FRAG_RESULT_DATA0); default: return false; } @@ -54,30 +54,23 @@ { nir_variable *out = NULL; nir_def *s; + int loc = -1; switch (intr->intrinsic) { case nir_intrinsic_store_deref: out = nir_intrinsic_get_var(intr, 0); + if (out->data.mode != nir_var_shader_out) + return false; + loc = out->data.location; break; case nir_intrinsic_store_output: - /* already had i/o lowered.. lookup the matching output var: */ - nir_foreach_shader_out_variable(var, shader) { - int drvloc = var->data.driver_location; - if (nir_intrinsic_base(intr) == drvloc) { - out = var; - break; - } - } - assume(out); + loc = nir_intrinsic_io_semantics(intr).location; break; default: return false; } - if (out->data.mode != nir_var_shader_out) - return false; - - if (is_color_output(shader, out)) { + if (is_color_output(shader, loc)) { b->cursor = nir_before_instr(&intr->instr); int src = intr->intrinsic == nir_intrinsic_store_deref ? 1 : 0; s = intr->src[src].ssa; diff -Nru mesa-24.0.3/src/compiler/nir/nir_lower_texcoord_replace.c mesa-24.0.5/src/compiler/nir/nir_lower_texcoord_replace.c --- mesa-24.0.3/src/compiler/nir/nir_lower_texcoord_replace.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/compiler/nir/nir_lower_texcoord_replace.c 2024-04-10 20:17:49.000000000 +0000 @@ -107,6 +107,7 @@ unsigned base = var->data.location - VARYING_SLOT_TEX0; b.cursor = nir_after_instr(instr); + uint32_t component_mask = BITFIELD_MASK(glsl_get_vector_elements(var->type)) << var->data.location_frac; nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]); nir_def *index = get_io_index(&b, deref); nir_def *mask = @@ -114,7 +115,7 @@ nir_iadd_imm(&b, index, base)); nir_def *cond = nir_test_mask(&b, mask, coord_replace); - nir_def *result = nir_bcsel(&b, cond, new_coord, + nir_def *result = nir_bcsel(&b, cond, nir_channels(&b, new_coord, component_mask), &intrin->def); nir_def_rewrite_uses_after(&intrin->def, diff -Nru mesa-24.0.3/src/compiler/nir/nir_serialize.c mesa-24.0.5/src/compiler/nir/nir_serialize.c --- mesa-24.0.3/src/compiler/nir/nir_serialize.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/compiler/nir/nir_serialize.c 2024-04-10 20:17:49.000000000 +0000 @@ -202,8 +202,6 @@ enum var_data_encoding { var_encode_full, - var_encode_shader_temp, - var_encode_function_temp, var_encode_location_diff, }; @@ -264,30 +262,23 @@ data.mode != nir_var_shader_out) data.location = 0; - /* Temporary variables don't serialize var->data. */ - if (data.mode == nir_var_shader_temp) - flags.u.data_encoding = var_encode_shader_temp; - else if (data.mode == nir_var_function_temp) - flags.u.data_encoding = var_encode_function_temp; - else { - struct nir_variable_data tmp = data; - - tmp.location = ctx->last_var_data.location; - tmp.location_frac = ctx->last_var_data.location_frac; - tmp.driver_location = ctx->last_var_data.driver_location; + struct nir_variable_data tmp = data; - /* See if we can encode only the difference in locations from the last - * variable. - */ - if (memcmp(&ctx->last_var_data, &tmp, sizeof(tmp)) == 0 && - abs((int)data.location - - (int)ctx->last_var_data.location) < (1 << 12) && - abs((int)data.driver_location - - (int)ctx->last_var_data.driver_location) < (1 << 15)) - flags.u.data_encoding = var_encode_location_diff; - else - flags.u.data_encoding = var_encode_full; - } + tmp.location = ctx->last_var_data.location; + tmp.location_frac = ctx->last_var_data.location_frac; + tmp.driver_location = ctx->last_var_data.driver_location; + + /* See if we can encode only the difference in locations from the last + * variable. + */ + if (memcmp(&ctx->last_var_data, &tmp, sizeof(tmp)) == 0 && + abs((int)data.location - + (int)ctx->last_var_data.location) < (1 << 12) && + abs((int)data.driver_location - + (int)ctx->last_var_data.driver_location) < (1 << 15)) + flags.u.data_encoding = var_encode_location_diff; + else + flags.u.data_encoding = var_encode_full; flags.u.ray_query = var->data.ray_query; @@ -306,27 +297,24 @@ if (flags.u.has_name) blob_write_string(ctx->blob, var->name); - if (flags.u.data_encoding == var_encode_full || - flags.u.data_encoding == var_encode_location_diff) { - if (flags.u.data_encoding == var_encode_full) { - blob_write_bytes(ctx->blob, &data, sizeof(data)); - } else { - /* Serialize only the difference in locations from the last variable. - */ - union packed_var_data_diff diff; - - diff.u.location = data.location - ctx->last_var_data.location; - diff.u.location_frac = data.location_frac - - ctx->last_var_data.location_frac; - diff.u.driver_location = data.driver_location - - ctx->last_var_data.driver_location; + if (flags.u.data_encoding == var_encode_full) { + blob_write_bytes(ctx->blob, &data, sizeof(data)); + } else { + /* Serialize only the difference in locations from the last variable. + */ + union packed_var_data_diff diff; - blob_write_uint32(ctx->blob, diff.u32); - } + diff.u.location = data.location - ctx->last_var_data.location; + diff.u.location_frac = data.location_frac - + ctx->last_var_data.location_frac; + diff.u.driver_location = data.driver_location - + ctx->last_var_data.driver_location; - ctx->last_var_data = data; + blob_write_uint32(ctx->blob, diff.u32); } + ctx->last_var_data = data; + for (unsigned i = 0; i < var->num_state_slots; i++) { blob_write_bytes(ctx->blob, &var->state_slots[i], sizeof(var->state_slots[i])); @@ -374,11 +362,7 @@ var->name = NULL; } - if (flags.u.data_encoding == var_encode_shader_temp) - var->data.mode = nir_var_shader_temp; - else if (flags.u.data_encoding == var_encode_function_temp) - var->data.mode = nir_var_function_temp; - else if (flags.u.data_encoding == var_encode_full) { + if (flags.u.data_encoding == var_encode_full) { blob_copy_bytes(ctx->blob, (uint8_t *)&var->data, sizeof(var->data)); ctx->last_var_data = var->data; } else { /* var_encode_location_diff */ diff -Nru mesa-24.0.3/src/freedreno/.gitlab-ci/reference/afuc_test.asm mesa-24.0.5/src/freedreno/.gitlab-ci/reference/afuc_test.asm --- mesa-24.0.3/src/freedreno/.gitlab-ci/reference/afuc_test.asm 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/freedreno/.gitlab-ci/reference/afuc_test.asm 2024-04-10 20:17:49.000000000 +0000 @@ -162,7 +162,6 @@ CP_BLIT: CP_BOOTSTRAP_UCODE: CP_COND_EXEC: -CP_COND_INDIRECT_BUFFER_PFE: CP_COND_REG_EXEC: CP_COND_WRITE5: CP_CONTEXT_REG_BUNCH: @@ -268,6 +267,7 @@ UNKN32: UNKN48: UNKN5: +UNKN58: UNKN6: UNKN7: UNKN73: diff -Nru mesa-24.0.3/src/freedreno/.gitlab-ci/traces/afuc_test.asm mesa-24.0.5/src/freedreno/.gitlab-ci/traces/afuc_test.asm --- mesa-24.0.3/src/freedreno/.gitlab-ci/traces/afuc_test.asm 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/freedreno/.gitlab-ci/traces/afuc_test.asm 2024-04-10 20:17:49.000000000 +0000 @@ -269,7 +269,7 @@ CP_INDIRECT_BUFFER_PFD: CP_DRAW_INDX_OFFSET: CP_REG_TEST: -CP_COND_INDIRECT_BUFFER_PFE: +UNKN58: CP_INVALIDATE_STATE: CP_WAIT_REG_MEM: CP_REG_TO_MEM: diff -Nru mesa-24.0.3/src/freedreno/registers/adreno/adreno_pm4.xml mesa-24.0.5/src/freedreno/registers/adreno/adreno_pm4.xml --- mesa-24.0.3/src/freedreno/registers/adreno/adreno_pm4.xml 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/freedreno/registers/adreno/adreno_pm4.xml 2024-04-10 20:17:49.000000000 +0000 @@ -371,7 +371,7 @@ Conditionally load a IB based on a flag, prefetch enabled - + Conditionally load a IB based on a flag, prefetch disabled Load a buffer with pre-fetch enabled @@ -648,6 +648,9 @@ Reset various on-chip state used for synchronization + + Invalidates the "CCHE" introduced on a740 + diff -Nru mesa-24.0.3/src/freedreno/vulkan/tu_cmd_buffer.cc mesa-24.0.5/src/freedreno/vulkan/tu_cmd_buffer.cc --- mesa-24.0.3/src/freedreno/vulkan/tu_cmd_buffer.cc 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/freedreno/vulkan/tu_cmd_buffer.cc 2024-04-10 20:17:49.000000000 +0000 @@ -187,6 +187,10 @@ .gfx_bindless = CHIP == A6XX ? 0x1f : 0xff, )); } + if (CHIP >= A7XX && (flushes & TU_CMD_FLAG_CCHE_INVALIDATE) && + /* Invalidating UCHE seems to also invalidate CCHE */ + !(flushes & TU_CMD_FLAG_CACHE_INVALIDATE)) + tu_cs_emit_pkt7(cs, CP_CCHE_INVALIDATE, 0); if (flushes & TU_CMD_FLAG_WAIT_MEM_WRITES) tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0); if (flushes & TU_CMD_FLAG_WAIT_FOR_IDLE) @@ -3246,6 +3250,13 @@ flush_bits |= TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE; } + /* There are multiple incoherent copies of CCHE, so any read through it may + * require invalidating it and we cannot optimize away invalidates. + */ + if (dst_mask & TU_ACCESS_CCHE_READ) { + flush_bits |= TU_CMD_FLAG_CCHE_INVALIDATE; + } + #undef DST_INCOHERENT_FLUSH cache->flush_bits |= flush_bits; @@ -3347,12 +3358,13 @@ VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT | VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT | SHADER_STAGES)) - mask |= TU_ACCESS_UCHE_READ; + mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_CCHE_READ; if (gfx_read_access(flags, stages, VK_ACCESS_2_DESCRIPTOR_BUFFER_READ_BIT_EXT, SHADER_STAGES)) { - mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_BINDLESS_DESCRIPTOR_READ; + mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_BINDLESS_DESCRIPTOR_READ | + TU_ACCESS_CCHE_READ; } if (gfx_write_access(flags, stages, diff -Nru mesa-24.0.3/src/freedreno/vulkan/tu_cmd_buffer.h mesa-24.0.5/src/freedreno/vulkan/tu_cmd_buffer.h --- mesa-24.0.3/src/freedreno/vulkan/tu_cmd_buffer.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/freedreno/vulkan/tu_cmd_buffer.h 2024-04-10 20:17:49.000000000 +0000 @@ -132,6 +132,13 @@ */ TU_ACCESS_BINDLESS_DESCRIPTOR_READ = 1 << 13, + /* The CCHE is a write-through cache which sits behind UCHE, with multiple + * incoherent copies. Because it's write-through we only have to worry + * about invalidating it for reads. It's invalidated by "ccinv" in the + * shader and CP_CCHE_INVALIDATE in the command stream. + */ + TU_ACCESS_CCHE_READ = 1 << 16, + TU_ACCESS_READ = TU_ACCESS_UCHE_READ | TU_ACCESS_CCU_COLOR_READ | @@ -139,7 +146,8 @@ TU_ACCESS_CCU_COLOR_INCOHERENT_READ | TU_ACCESS_CCU_DEPTH_INCOHERENT_READ | TU_ACCESS_SYSMEM_READ | - TU_ACCESS_BINDLESS_DESCRIPTOR_READ, + TU_ACCESS_BINDLESS_DESCRIPTOR_READ | + TU_ACCESS_CCHE_READ, TU_ACCESS_WRITE = TU_ACCESS_UCHE_WRITE | @@ -186,10 +194,11 @@ TU_CMD_FLAG_CCU_INVALIDATE_COLOR = 1 << 3, TU_CMD_FLAG_CACHE_FLUSH = 1 << 4, TU_CMD_FLAG_CACHE_INVALIDATE = 1 << 5, - TU_CMD_FLAG_WAIT_MEM_WRITES = 1 << 6, - TU_CMD_FLAG_WAIT_FOR_IDLE = 1 << 7, - TU_CMD_FLAG_WAIT_FOR_ME = 1 << 8, - TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE = 1 << 9, + TU_CMD_FLAG_CCHE_INVALIDATE = 1 << 6, + TU_CMD_FLAG_WAIT_MEM_WRITES = 1 << 7, + TU_CMD_FLAG_WAIT_FOR_IDLE = 1 << 8, + TU_CMD_FLAG_WAIT_FOR_ME = 1 << 9, + TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE = 1 << 10, TU_CMD_FLAG_ALL_FLUSH = TU_CMD_FLAG_CCU_FLUSH_DEPTH | @@ -205,6 +214,7 @@ TU_CMD_FLAG_CCU_INVALIDATE_COLOR | TU_CMD_FLAG_CACHE_INVALIDATE | TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE | + TU_CMD_FLAG_CCHE_INVALIDATE | /* Treat CP_WAIT_FOR_ME as a "cache" that needs to be invalidated when a * a command that needs CP_WAIT_FOR_ME is executed. This means we may * insert an extra WAIT_FOR_ME before an indirect command requiring it diff -Nru mesa-24.0.3/src/freedreno/vulkan/tu_shader.cc mesa-24.0.5/src/freedreno/vulkan/tu_shader.cc --- mesa-24.0.3/src/freedreno/vulkan/tu_shader.cc 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/freedreno/vulkan/tu_shader.cc 2024-04-10 20:17:49.000000000 +0000 @@ -2104,20 +2104,21 @@ struct blob_reader *blob); static void -tu_shader_destroy(struct vk_device *device, - struct vk_pipeline_cache_object *object) +tu_shader_pipeline_cache_object_destroy(struct vk_device *vk_device, + struct vk_pipeline_cache_object *object) { + struct tu_device *device = container_of(vk_device, struct tu_device, vk); struct tu_shader *shader = container_of(object, struct tu_shader, base); vk_pipeline_cache_object_finish(&shader->base); - vk_free(&device->alloc, shader); + tu_shader_destroy(device, shader); } const struct vk_pipeline_cache_object_ops tu_shader_ops = { .serialize = tu_shader_serialize, .deserialize = tu_shader_deserialize, - .destroy = tu_shader_destroy, + .destroy = tu_shader_pipeline_cache_object_destroy, }; static struct tu_shader * @@ -2376,6 +2377,8 @@ executable_info); } + ir3_shader_destroy(ir3_shader); + shader->view_mask = key->multiview_mask; switch (shader->variant->type) { @@ -2778,6 +2781,7 @@ struct ir3_shader *ir3_shader = ir3_shader_from_nir(dev->compiler, fs_b.shader, &options, &so_info); (*shader)->variant = ir3_shader_create_variant(ir3_shader, &key, false); + ir3_shader_destroy(ir3_shader); return tu_upload_shader(dev, *shader); } @@ -2846,5 +2850,10 @@ if (shader->pvtmem_bo) tu_bo_finish(dev, shader->pvtmem_bo); + if (shader->variant) + ralloc_free((void *)shader->variant); + if (shader->safe_const_variant) + ralloc_free((void *)shader->safe_const_variant); + vk_free(&dev->vk.alloc, shader); } diff -Nru mesa-24.0.3/src/gallium/auxiliary/gallivm/lp_bld_init.c mesa-24.0.5/src/gallium/auxiliary/gallivm/lp_bld_init.c --- mesa-24.0.3/src/gallium/auxiliary/gallivm/lp_bld_init.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/auxiliary/gallivm/lp_bld_init.c 2024-04-10 20:17:49.000000000 +0000 @@ -609,7 +609,11 @@ LLVMRunPasses(gallivm->module, passes, LLVMGetExecutionEngineTargetMachine(gallivm->engine), opts); if (!(gallivm_perf & GALLIVM_PERF_NO_OPT)) +#if LLVM_VERSION_MAJOR >= 18 + strcpy(passes, "sroa,early-cse,simplifycfg,reassociate,mem2reg,instsimplify,instcombine"); +#else strcpy(passes, "sroa,early-cse,simplifycfg,reassociate,mem2reg,instsimplify,instcombine"); +#endif else strcpy(passes, "mem2reg"); diff -Nru mesa-24.0.3/src/gallium/drivers/etnaviv/etnaviv_rs.c mesa-24.0.5/src/gallium/drivers/etnaviv/etnaviv_rs.c --- mesa-24.0.3/src/gallium/drivers/etnaviv/etnaviv_rs.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/etnaviv/etnaviv_rs.c 2024-04-10 20:17:49.000000000 +0000 @@ -711,12 +711,17 @@ width = align(width, w_align); if (height & (h_align - 1) && height >= src_lev->height * src_yscale && height >= dst_lev->height) { - if (!ctx->screen->specs.single_buffer && - align(height, h_align * ctx->screen->specs.pixel_pipes) <= - dst_lev->padded_height * src_yscale) - height = align(height, h_align * ctx->screen->specs.pixel_pipes); - else - height = align(height, h_align); + height = align(height, h_align); + + /* Try to increase alignment to multi-pipe requirements to unlock + * multi-pipe resolve for increased performance. */ + if (!ctx->screen->specs.single_buffer) { + unsigned int pipe_align = align(height, h_align * ctx->screen->specs.pixel_pipes); + + if (pipe_align <= src_lev->padded_height && + pipe_align <= dst_lev->padded_height * src_yscale) + height = pipe_align; + } } /* The padded dimensions are in samples */ diff -Nru mesa-24.0.3/src/gallium/drivers/etnaviv/etnaviv_util.h mesa-24.0.5/src/gallium/drivers/etnaviv/etnaviv_util.h --- mesa-24.0.3/src/gallium/drivers/etnaviv/etnaviv_util.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/etnaviv/etnaviv_util.h 2024-04-10 20:17:49.000000000 +0000 @@ -35,14 +35,14 @@ static inline uint32_t etna_float_to_fixp55(float f) { - return U_FIXED(f, 5); + return S_FIXED(f, 5); } /* float to fixp 8.8 */ static inline uint32_t etna_float_to_fixp88(float f) { - return U_FIXED(f, 8); + return S_FIXED(f, 8); } /* texture size to log2 in fixp 5.5 format */ diff -Nru mesa-24.0.3/src/gallium/drivers/etnaviv/etnaviv_zsa.c mesa-24.0.5/src/gallium/drivers/etnaviv/etnaviv_zsa.c --- mesa-24.0.3/src/gallium/drivers/etnaviv/etnaviv_zsa.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/etnaviv/etnaviv_zsa.c 2024-04-10 20:17:49.000000000 +0000 @@ -48,7 +48,7 @@ cs->base = *so; cs->z_test_enabled = so->depth_enabled && so->depth_func != PIPE_FUNC_ALWAYS; - cs->z_write_enabled = so->depth_enabled && so->depth_writemask; + cs->z_write_enabled = so->depth_writemask; /* XXX does stencil[0] / stencil[1] order depend on rs->front_ccw? */ diff -Nru mesa-24.0.3/src/gallium/drivers/iris/iris_batch.c mesa-24.0.5/src/gallium/drivers/iris/iris_batch.c --- mesa-24.0.3/src/gallium/drivers/iris/iris_batch.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/iris/iris_batch.c 2024-04-10 20:17:49.000000000 +0000 @@ -862,8 +862,8 @@ return names[name]; } -static inline bool -context_or_exec_queue_was_banned(struct iris_bufmgr *bufmgr, int ret) +bool +iris_batch_is_banned(struct iris_bufmgr *bufmgr, int ret) { enum intel_kmd_type kmd_type = iris_bufmgr_get_device_info(bufmgr)->kmd_type; @@ -960,7 +960,7 @@ * has been lost and needs to be re-initialized. If this succeeds, * dubiously claim success... */ - if (ret && context_or_exec_queue_was_banned(bufmgr, ret)) { + if (ret && iris_batch_is_banned(bufmgr, ret)) { enum pipe_reset_status status = iris_batch_check_for_reset(batch); if (status != PIPE_NO_RESET || ice->context_reset_signaled) diff -Nru mesa-24.0.3/src/gallium/drivers/iris/iris_batch.h mesa-24.0.5/src/gallium/drivers/iris/iris_batch.h --- mesa-24.0.3/src/gallium/drivers/iris/iris_batch.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/iris/iris_batch.h 2024-04-10 20:17:49.000000000 +0000 @@ -446,6 +446,9 @@ const char * iris_batch_name_to_string(enum iris_batch_name name); +bool +iris_batch_is_banned(struct iris_bufmgr *bufmgr, int ret); + #define iris_foreach_batch(ice, batch) \ for (struct iris_batch *batch = &ice->batches[0]; \ batch <= &ice->batches[((struct iris_screen *)ice->ctx.screen)->devinfo->ver >= 12 ? IRIS_BATCH_BLITTER : IRIS_BATCH_COMPUTE]; \ diff -Nru mesa-24.0.3/src/gallium/drivers/iris/iris_state.c mesa-24.0.5/src/gallium/drivers/iris/iris_state.c --- mesa-24.0.3/src/gallium/drivers/iris/iris_state.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/iris/iris_state.c 2024-04-10 20:17:49.000000000 +0000 @@ -9537,10 +9537,12 @@ /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */ if (IS_COMPUTE_PIPELINE(batch)) { - if ((GFX_VER == 9 || GFX_VER == 11) && - (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { - /* Project: SKL, ICL / Argument: Tex Invalidate - * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." + if (GFX_VER >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { + /* SKL PRMs, Volume 7: 3D-Media-GPGPU, Programming Restrictions for + * PIPE_CONTROL, Flush Types: + * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." + * For newer platforms this is documented in the PIPE_CONTROL + * instruction page. */ flags |= PIPE_CONTROL_CS_STALL; } diff -Nru mesa-24.0.3/src/gallium/drivers/iris/xe/iris_batch.c mesa-24.0.5/src/gallium/drivers/iris/xe/iris_batch.c --- mesa-24.0.3/src/gallium/drivers/iris/xe/iris_batch.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/iris/xe/iris_batch.c 2024-04-10 20:17:49.000000000 +0000 @@ -151,7 +151,45 @@ free(engines_info); } -void iris_xe_destroy_batch(struct iris_batch *batch) +/* + * Wait for all previous DRM_IOCTL_XE_EXEC calls over the + * drm_xe_exec_queue in this iris_batch to complete. + **/ +static void +iris_xe_wait_exec_queue_idle(struct iris_batch *batch) +{ + struct iris_bufmgr *bufmgr = batch->screen->bufmgr; + struct iris_syncobj *syncobj = iris_create_syncobj(bufmgr); + struct drm_xe_sync xe_sync = { + .type = DRM_XE_SYNC_TYPE_SYNCOBJ, + .flags = DRM_XE_SYNC_FLAG_SIGNAL, + }; + struct drm_xe_exec exec = { + .exec_queue_id = batch->xe.exec_queue_id, + .num_syncs = 1, + .syncs = (uintptr_t)&xe_sync, + }; + int ret; + + if (!syncobj) + return; + + xe_sync.handle = syncobj->handle; + /* Using the special exec.num_batch_buffer == 0 handling to get syncobj + * signaled when the last DRM_IOCTL_XE_EXEC is completed. + */ + ret = intel_ioctl(iris_bufmgr_get_fd(bufmgr), DRM_IOCTL_XE_EXEC, &exec); + if (ret == 0) { + assert(iris_wait_syncobj(bufmgr, syncobj, INT64_MAX)); + } else { + assert(iris_batch_is_banned(bufmgr, errno) == true); + } + + iris_syncobj_destroy(bufmgr, syncobj); +} + +static void +iris_xe_destroy_exec_queue(struct iris_batch *batch) { struct iris_screen *screen = batch->screen; struct iris_bufmgr *bufmgr = screen->bufmgr; @@ -165,6 +203,15 @@ assert(ret == 0); } +void iris_xe_destroy_batch(struct iris_batch *batch) +{ + /* Xe KMD don't refcount anything, so resources could be freed while they + * are still in use if we don't wait for exec_queue to be idle. + */ + iris_xe_wait_exec_queue_idle(batch); + iris_xe_destroy_exec_queue(batch); +} + bool iris_xe_replace_batch(struct iris_batch *batch) { enum intel_engine_class engine_classes[IRIS_BATCH_COUNT]; @@ -184,7 +231,7 @@ ret = iris_xe_init_batch(bufmgr, engines_info, engine_classes[batch->name], ice->priority, &new_exec_queue_id); if (ret) { - iris_xe_destroy_batch(batch); + iris_xe_destroy_exec_queue(batch); batch->xe.exec_queue_id = new_exec_queue_id; iris_lost_context_state(batch); } diff -Nru mesa-24.0.3/src/gallium/drivers/llvmpipe/lp_screen.c mesa-24.0.5/src/gallium/drivers/llvmpipe/lp_screen.c --- mesa-24.0.3/src/gallium/drivers/llvmpipe/lp_screen.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/llvmpipe/lp_screen.c 2024-04-10 20:17:49.000000000 +0000 @@ -410,6 +410,11 @@ return PIPE_MAX_SHADER_SAMPLER_VIEWS; else return 0; + case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: + if (debug_get_bool_option("DRAW_USE_LLVM", false)) + return LP_MAX_TGSI_CONST_BUFFERS; + else + return draw_get_shader_param(shader, param); default: return draw_get_shader_param(shader, param); } diff -Nru mesa-24.0.3/src/gallium/drivers/nouveau/nouveau_screen.c mesa-24.0.5/src/gallium/drivers/nouveau/nouveau_screen.c --- mesa-24.0.3/src/gallium/drivers/nouveau/nouveau_screen.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/nouveau/nouveau_screen.c 2024-04-10 20:17:49.000000000 +0000 @@ -291,6 +291,8 @@ void *data; union nouveau_bo_config mm_config; + glsl_type_singleton_init_or_ref(); + char *nv_dbg = getenv("NOUVEAU_MESA_DEBUG"); if (nv_dbg) nouveau_mesa_debug = atoi(nv_dbg); @@ -442,8 +444,6 @@ &mm_config); screen->mm_VRAM = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config); - glsl_type_singleton_init_or_ref(); - return 0; err: diff -Nru mesa-24.0.3/src/gallium/drivers/panfrost/pan_cmdstream.c mesa-24.0.5/src/gallium/drivers/panfrost/pan_cmdstream.c --- mesa-24.0.3/src/gallium/drivers/panfrost/pan_cmdstream.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/panfrost/pan_cmdstream.c 2024-04-10 20:17:49.000000000 +0000 @@ -3021,6 +3021,11 @@ mali_ptr saved_tls = batch->tls.gpu; batch->tls.gpu = panfrost_emit_shared_memory(batch, info); + /* if indirect, mark the indirect buffer as being read */ + if (info->indirect) + panfrost_batch_read_rsrc(batch, pan_resource(info->indirect), PIPE_SHADER_COMPUTE); + + /* launch it */ JOBX(launch_grid)(batch, info); batch->compute_count++; batch->tls.gpu = saved_tls; diff -Nru mesa-24.0.3/src/gallium/drivers/r300/compiler/r500_nir_lower_fcsel.c mesa-24.0.5/src/gallium/drivers/r300/compiler/r500_nir_lower_fcsel.c --- mesa-24.0.3/src/gallium/drivers/r300/compiler/r500_nir_lower_fcsel.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/r300/compiler/r500_nir_lower_fcsel.c 2024-04-10 20:17:49.000000000 +0000 @@ -1,3 +1,8 @@ +/* + * Copyright Pavel Ondračka + * SPDX-License-Identifier: MIT + */ + #include #include "r300_nir.h" #include "nir_builder.h" diff -Nru mesa-24.0.3/src/gallium/drivers/r300/r300_fs.c mesa-24.0.5/src/gallium/drivers/r300/r300_fs.c --- mesa-24.0.3/src/gallium/drivers/r300/r300_fs.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/r300/r300_fs.c 2024-04-10 20:17:49.000000000 +0000 @@ -526,6 +526,7 @@ } free(compiler.code->constants.Constants); + free(compiler.code->constants_remap_table); rc_destroy(&compiler.Base); r300_dummy_fragment_shader(r300, shader); return; diff -Nru mesa-24.0.3/src/gallium/drivers/r300/r300_public.h mesa-24.0.5/src/gallium/drivers/r300/r300_public.h --- mesa-24.0.3/src/gallium/drivers/r300/r300_public.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/r300/r300_public.h 2024-04-10 20:17:49.000000000 +0000 @@ -1,4 +1,4 @@ - +// SPDX-License-Identifier: MIT #ifndef R300_PUBLIC_H #define R300_PUBLIC_H diff -Nru mesa-24.0.3/src/gallium/drivers/r300/r300_texture.c mesa-24.0.5/src/gallium/drivers/r300/r300_texture.c --- mesa-24.0.3/src/gallium/drivers/r300/r300_texture.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/r300/r300_texture.c 2024-04-10 20:17:49.000000000 +0000 @@ -1223,7 +1223,8 @@ tex->b.nr_samples, tex->tex.microtile, tex->tex.macrotile[level], - DIM_HEIGHT, 0); + DIM_HEIGHT, 0, + tex->b.bind & PIPE_BIND_SCANOUT); surface->cbzb_height = align((surface->base.height + 1) / 2, tile_height); diff -Nru mesa-24.0.3/src/gallium/drivers/r300/r300_texture_desc.c mesa-24.0.5/src/gallium/drivers/r300/r300_texture_desc.c --- mesa-24.0.3/src/gallium/drivers/r300/r300_texture_desc.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/r300/r300_texture_desc.c 2024-04-10 20:17:49.000000000 +0000 @@ -33,7 +33,8 @@ unsigned num_samples, enum radeon_bo_layout microtile, enum radeon_bo_layout macrotile, - enum r300_dim dim, bool is_rs690) + enum r300_dim dim, bool is_rs690, + bool scanout) { static const unsigned table[2][5][3][2] = { @@ -75,6 +76,13 @@ tile = align; } + if (scanout) { + if (microtile || macrotile) + tile = MAX2(tile, 256 / pixsize); + else + tile = MAX2(tile, 64); + } + assert(tile); return tile; } @@ -92,7 +100,9 @@ } tile = r300_get_pixel_alignment(tex->b.format, tex->b.nr_samples, - tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0); + tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0, + tex->b.bind & PIPE_BIND_SCANOUT); + if (dim == DIM_WIDTH) { texdim = u_minify(tex->tex.width0, level); } else { @@ -133,11 +143,16 @@ width = u_minify(tex->tex.width0, level); if (util_format_is_plain(tex->b.format)) { + /* MSAA and mipmapping are incompatible with scanout. */ + assert(!(tex->b.bind & PIPE_BIND_SCANOUT) || + (tex->b.last_level == 0 && tex->b.nr_samples <= 1)); + tile_width = r300_get_pixel_alignment(tex->b.format, tex->b.nr_samples, tex->tex.microtile, tex->tex.macrotile[level], - DIM_WIDTH, is_rs690); + DIM_WIDTH, is_rs690, + tex->b.bind & PIPE_BIND_SCANOUT); width = align(width, tile_width); stride = util_format_get_stride(tex->b.format, width); @@ -169,7 +184,8 @@ tex->b.nr_samples, tex->tex.microtile, tex->tex.macrotile[level], - DIM_HEIGHT, 0); + DIM_HEIGHT, 0, + tex->b.bind & PIPE_BIND_SCANOUT); height = align(height, tile_height); /* See if the CBZB clear can be used on the buffer, @@ -259,6 +275,11 @@ tex->tex.stride_in_bytes[i] = stride; tex->tex.cbzb_allowed[i] = tex->tex.cbzb_allowed[i] && aligned_for_cbzb; + if (tex->b.bind & PIPE_BIND_SCANOUT) { + assert(i == 0); + tex->tex.stride_in_bytes_override = stride; + } + SCREEN_DBG(screen, DBG_TEXALLOC, "r300: Texture miptree: Level %d " "(%dx%dx%d px, pitch %d bytes) %d bytes total, macrotiled %s\n", i, u_minify(tex->tex.width0, i), u_minify(tex->tex.height0, i), diff -Nru mesa-24.0.3/src/gallium/drivers/r300/r300_texture_desc.h mesa-24.0.5/src/gallium/drivers/r300/r300_texture_desc.h --- mesa-24.0.3/src/gallium/drivers/r300/r300_texture_desc.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/r300/r300_texture_desc.h 2024-04-10 20:17:49.000000000 +0000 @@ -41,7 +41,8 @@ unsigned num_samples, enum radeon_bo_layout microtile, enum radeon_bo_layout macrotile, - enum r300_dim dim, bool is_rs690); + enum r300_dim dim, bool is_rs690, + bool scanout); void r300_texture_desc_init(struct r300_screen *rscreen, struct r300_resource *tex, diff -Nru mesa-24.0.3/src/gallium/drivers/r600/r600_formats.h mesa-24.0.5/src/gallium/drivers/r600/r600_formats.h --- mesa-24.0.3/src/gallium/drivers/r600/r600_formats.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/r600/r600_formats.h 2024-04-10 20:17:49.000000000 +0000 @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT #ifndef R600_FORMATS_H #define R600_FORMATS_H diff -Nru mesa-24.0.3/src/gallium/drivers/r600/r600_opcodes.h mesa-24.0.5/src/gallium/drivers/r600/r600_opcodes.h --- mesa-24.0.3/src/gallium/drivers/r600/r600_opcodes.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/r600/r600_opcodes.h 2024-04-10 20:17:49.000000000 +0000 @@ -1,4 +1,4 @@ - +// SPDX-License-Identifier: MIT #ifndef R600_OPCODES_H #define R600_OPCODES_H diff -Nru mesa-24.0.3/src/gallium/drivers/r600/sfn/sfn_shader_gs.h mesa-24.0.5/src/gallium/drivers/r600/sfn/sfn_shader_gs.h --- mesa-24.0.3/src/gallium/drivers/r600/sfn/sfn_shader_gs.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/r600/sfn/sfn_shader_gs.h 2024-04-10 20:17:49.000000000 +0000 @@ -1,3 +1,9 @@ +/* + * Copyright 2021 Collabora LTD + * Author: Gert Wollny + * SPDX-License-Identifier: MIT + */ + #ifndef SFN_GEOMETRYSHADER_H #define SFN_GEOMETRYSHADER_H diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/radeon_vcn_enc.c mesa-24.0.5/src/gallium/drivers/radeonsi/radeon_vcn_enc.c --- mesa-24.0.3/src/gallium/drivers/radeonsi/radeon_vcn_enc.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/radeon_vcn_enc.c 2024-04-10 20:17:49.000000000 +0000 @@ -196,9 +196,9 @@ enc->enc_pic.crop_bottom = pic->seq.enc_frame_crop_bottom_offset; } else { enc->enc_pic.crop_left = 0; - enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2; + enc->enc_pic.crop_right = 0; enc->enc_pic.crop_top = 0; - enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2; + enc->enc_pic.crop_bottom = 0; } } @@ -445,9 +445,9 @@ enc->enc_pic.crop_bottom = pic->seq.conf_win_bottom_offset; } else { enc->enc_pic.crop_left = 0; - enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2; + enc->enc_pic.crop_right = 0; enc->enc_pic.crop_top = 0; - enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2; + enc->enc_pic.crop_bottom = 0; } } diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c mesa-24.0.5/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c --- mesa-24.0.3/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c 2024-04-10 20:17:49.000000000 +0000 @@ -81,10 +81,12 @@ enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64); } enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); + enc->enc_pic.session_init.padding_width = - enc->enc_pic.session_init.aligned_picture_width - enc->base.width; + (enc->enc_pic.crop_left + enc->enc_pic.crop_right) * 2; enc->enc_pic.session_init.padding_height = - enc->enc_pic.session_init.aligned_picture_height - enc->base.height; + (enc->enc_pic.crop_top + enc->enc_pic.crop_bottom) * 2; + enc->enc_pic.session_init.display_remote = 0; enc->enc_pic.session_init.pre_encode_mode = enc->enc_pic.quality_modes.pre_encode_mode; enc->enc_pic.session_init.pre_encode_chroma_enabled = !!(enc->enc_pic.quality_modes.pre_encode_mode); diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/radeon_vcn_enc_3_0.c mesa-24.0.5/src/gallium/drivers/radeonsi/radeon_vcn_enc_3_0.c --- mesa-24.0.3/src/gallium/drivers/radeonsi/radeon_vcn_enc_3_0.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/radeon_vcn_enc_3_0.c 2024-04-10 20:17:49.000000000 +0000 @@ -506,10 +506,12 @@ enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64); } enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); + enc->enc_pic.session_init.padding_width = - enc->enc_pic.session_init.aligned_picture_width - enc->base.width; + (enc->enc_pic.crop_left + enc->enc_pic.crop_right) * 2; enc->enc_pic.session_init.padding_height = - enc->enc_pic.session_init.aligned_picture_height - enc->base.height; + (enc->enc_pic.crop_top + enc->enc_pic.crop_bottom) * 2; + enc->enc_pic.session_init.slice_output_enabled = 0; enc->enc_pic.session_init.display_remote = 0; enc->enc_pic.session_init.pre_encode_mode = enc->enc_pic.quality_modes.pre_encode_mode; diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c mesa-24.0.5/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c --- mesa-24.0.3/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c 2024-04-10 20:17:49.000000000 +0000 @@ -81,7 +81,6 @@ static void radeon_enc_session_init(struct radeon_encoder *enc) { - bool av1_encoding = false; uint32_t av1_height = enc->enc_pic.pic_height_in_luma_samples; switch (u_reduce_video_profile(enc->base.profile)) { @@ -89,11 +88,20 @@ enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264; enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16); enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); + + enc->enc_pic.session_init.padding_width = + (enc->enc_pic.crop_left + enc->enc_pic.crop_right) * 2; + enc->enc_pic.session_init.padding_height = + (enc->enc_pic.crop_top + enc->enc_pic.crop_bottom) * 2; break; case PIPE_VIDEO_FORMAT_HEVC: enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC; enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64); enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); + enc->enc_pic.session_init.padding_width = + (enc->enc_pic.crop_left + enc->enc_pic.crop_right) * 2; + enc->enc_pic.session_init.padding_height = + (enc->enc_pic.crop_top + enc->enc_pic.crop_bottom) * 2; break; case PIPE_VIDEO_FORMAT_AV1: enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_AV1; @@ -104,33 +112,24 @@ if (!(av1_height % 8) && (av1_height % 16) && !(enc->enc_pic.enable_render_size)) enc->enc_pic.session_init.aligned_picture_height = av1_height + 2; - av1_encoding = true; + enc->enc_pic.session_init.padding_width = + enc->enc_pic.session_init.aligned_picture_width - + enc->enc_pic.pic_width_in_luma_samples; + enc->enc_pic.session_init.padding_height = + enc->enc_pic.session_init.aligned_picture_height - av1_height; + + if (enc->enc_pic.enable_render_size) + enc->enc_pic.enable_render_size = + (enc->enc_pic.session_init.aligned_picture_width != + enc->enc_pic.render_width) || + (enc->enc_pic.session_init.aligned_picture_height != + enc->enc_pic.render_height); break; default: assert(0); break; } - enc->enc_pic.session_init.padding_width = - enc->enc_pic.session_init.aligned_picture_width - enc->base.width; - enc->enc_pic.session_init.padding_height = - enc->enc_pic.session_init.aligned_picture_height - enc->base.height; - - if (av1_encoding) { - enc->enc_pic.session_init.padding_width = - enc->enc_pic.session_init.aligned_picture_width - - enc->enc_pic.pic_width_in_luma_samples; - enc->enc_pic.session_init.padding_height = - enc->enc_pic.session_init.aligned_picture_height - av1_height; - - if (enc->enc_pic.enable_render_size) - enc->enc_pic.enable_render_size = - (enc->enc_pic.session_init.aligned_picture_width != - enc->enc_pic.render_width) || - (enc->enc_pic.session_init.aligned_picture_height != - enc->enc_pic.render_height); - } - enc->enc_pic.session_init.slice_output_enabled = 0; enc->enc_pic.session_init.display_remote = 0; enc->enc_pic.session_init.pre_encode_mode = enc->enc_pic.quality_modes.pre_encode_mode; diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/si_get.c mesa-24.0.5/src/gallium/drivers/radeonsi/si_get.c --- mesa-24.0.3/src/gallium/drivers/radeonsi/si_get.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/si_get.c 2024-04-10 20:17:49.000000000 +0000 @@ -838,6 +838,18 @@ } else return 0; + case PIPE_VIDEO_CAP_ENC_SURFACE_ALIGNMENT: + if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN || + profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) { + union pipe_enc_cap_surface_alignment attrib; + attrib.value = 0; + + attrib.bits.log2_width_alignment = RADEON_ENC_HEVC_SURFACE_LOG2_WIDTH_ALIGNMENT; + attrib.bits.log2_height_alignment = RADEON_ENC_HEVC_SURFACE_LOG2_HEIGHT_ALIGNMENT; + return attrib.value; + } + else + return 0; default: return 0; diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/si_shader.c mesa-24.0.5/src/gallium/drivers/radeonsi/si_shader.c --- mesa-24.0.3/src/gallium/drivers/radeonsi/si_shader.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/si_shader.c 2024-04-10 20:17:49.000000000 +0000 @@ -1770,6 +1770,11 @@ assert(nir_intrinsic_component(intr) == 0); unsigned cb_shader_mask = ac_get_cb_shader_mask(key->ps.part.epilog.spi_shader_col_format); + /* Preserve alpha if ALPHA_TESTING is enabled. */ + if (key->ps.part.epilog.alpha_func != PIPE_FUNC_ALWAYS || + key->ps.part.epilog.alpha_to_coverage_via_mrtz) + cb_shader_mask |= 1 << 3; + /* If COLOR is broadcasted to multiple color buffers, combine their masks. */ if (location == FRAG_RESULT_COLOR) { for (unsigned i = 1; i <= key->ps.part.epilog.last_cbuf; i++) diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/si_shader_llvm.c mesa-24.0.5/src/gallium/drivers/radeonsi/si_shader_llvm.c --- mesa-24.0.3/src/gallium/drivers/radeonsi/si_shader_llvm.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/si_shader_llvm.c 2024-04-10 20:17:49.000000000 +0000 @@ -239,7 +239,6 @@ /* Run the pass */ LLVMRunPassManager(ctx->compiler->passmgr, ctx->ac.module); - LLVMDisposeBuilder(ctx->ac.builder); } void si_llvm_dispose(struct si_shader_context *ctx) diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/si_shaderlib_nir.c mesa-24.0.5/src/gallium/drivers/radeonsi/si_shaderlib_nir.c --- mesa-24.0.3/src/gallium/drivers/radeonsi/si_shaderlib_nir.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/si_shaderlib_nir.c 2024-04-10 20:17:49.000000000 +0000 @@ -697,13 +697,15 @@ * the 2nd store writes into 1 * wavesize + tid, * the 3rd store writes into 2 * wavesize + tid, etc. */ - nir_def *store_address = get_global_ids(&b, 1); + nir_def *store_address = + nir_iadd(&b, nir_imul_imm(&b, nir_channel(&b, nir_load_workgroup_id(&b), 0), + default_wave_size * num_mem_ops), + nir_channel(&b, nir_load_local_invocation_id(&b), 0)); /* Convert from a "store size unit" into bytes. */ store_address = nir_imul_imm(&b, store_address, 4 * inst_dwords[0]); - nir_def *load_address = store_address, *value, *values[num_mem_ops]; - value = nir_undef(&b, 1, 32); + nir_def *load_address = store_address, *value = NULL, *values[num_mem_ops]; if (is_copy) { b.shader->info.num_ssbos++; @@ -723,7 +725,7 @@ load_address = nir_iadd(&b, load_address, nir_imm_int(&b, 4 * inst_dwords[i] * default_wave_size)); } - values[i] = nir_load_ssbo(&b, 4, 32, nir_imm_int(&b, 1),load_address, + values[i] = nir_load_ssbo(&b, inst_dwords[i], 32, nir_imm_int(&b, 1), load_address, .access = load_qualifier); } diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/si_state.c mesa-24.0.5/src/gallium/drivers/radeonsi/si_state.c --- mesa-24.0.3/src/gallium/drivers/radeonsi/si_state.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/si_state.c 2024-04-10 20:17:49.000000000 +0000 @@ -6286,11 +6286,10 @@ /* Compute registers. */ si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, S_00B834_DATA(sscreen->info.address32_hi >> 8)); - si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, compute_cu_en); - si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1, compute_cu_en); - si_pm4_set_reg(pm4, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, compute_cu_en); - si_pm4_set_reg(pm4, R_00B868_COMPUTE_STATIC_THREAD_MGMT_SE3, compute_cu_en); + for (unsigned i = 0; i < 4; ++i) + si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 + i * 4, + i < sscreen->info.num_se ? compute_cu_en : 0x0); si_pm4_set_reg(pm4, R_00B890_COMPUTE_USER_ACCUM_0, 0); si_pm4_set_reg(pm4, R_00B894_COMPUTE_USER_ACCUM_1, 0); @@ -6298,10 +6297,9 @@ si_pm4_set_reg(pm4, R_00B89C_COMPUTE_USER_ACCUM_3, 0); if (sctx->gfx_level >= GFX11) { - si_pm4_set_reg(pm4, R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4, compute_cu_en); - si_pm4_set_reg(pm4, R_00B8B0_COMPUTE_STATIC_THREAD_MGMT_SE5, compute_cu_en); - si_pm4_set_reg(pm4, R_00B8B4_COMPUTE_STATIC_THREAD_MGMT_SE6, compute_cu_en); - si_pm4_set_reg(pm4, R_00B8B8_COMPUTE_STATIC_THREAD_MGMT_SE7, compute_cu_en); + for (unsigned i = 4; i < 8; ++i) + si_pm4_set_reg(pm4, R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4 + (i - 4) * 4, + i < sscreen->info.num_se ? compute_cu_en : 0x0); /* How many threads should go to 1 SE before moving onto the next. Think of GL1 cache hits. * Only these values are valid: 0 (disabled), 64, 128, 256, 512 @@ -6392,6 +6390,7 @@ (sctx->gfx_level >= GFX11 ? S_028410_DCC_WR_POLICY_GFX11(meta_write_policy) | S_028410_COLOR_WR_POLICY_GFX11(V_028410_CACHE_STREAM) | + S_028410_DCC_RD_POLICY(meta_read_policy) | S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX11) : S_028410_CMASK_WR_POLICY(meta_write_policy) | @@ -6401,7 +6400,7 @@ S_028410_CMASK_RD_POLICY(meta_read_policy) | S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_GFX10) | S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX10)) | - S_028410_DCC_RD_POLICY(meta_read_policy)); + S_028410_DCC_RD_POLICY(meta_read_policy)); si_pm4_set_reg(pm4, R_028708_SPI_SHADER_IDX_FORMAT, S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP)); @@ -6445,8 +6444,10 @@ S_028B50_DONUT_SPLIT_GFX9(24) | S_028B50_TRAP_SPLIT(6)); + /* GFX11+ shouldn't subtract 1 from pbb_max_alloc_count. */ + unsigned gfx10_one = sctx->gfx_level < GFX11; si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, - S_028C48_MAX_ALLOC_COUNT(sscreen->info.pbb_max_alloc_count - 1) | + S_028C48_MAX_ALLOC_COUNT(sscreen->info.pbb_max_alloc_count - gfx10_one) | S_028C48_MAX_PRIM_PER_BATCH(1023)); if (sctx->gfx_level >= GFX11_5) diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/si_state.h mesa-24.0.5/src/gallium/drivers/radeonsi/si_state.h --- mesa-24.0.3/src/gallium/drivers/radeonsi/si_state.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/si_state.h 2024-04-10 20:17:49.000000000 +0000 @@ -342,7 +342,7 @@ /* The slots below can be reused by other generations. */ SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, /* GFX6-8 (GFX9+ can reuse this slot) */ - SI_TRACKED_VGT_REUSE_OFF, /* GFX6-8 (GFX9+ can reuse this slot) */ + SI_TRACKED_VGT_REUSE_OFF, /* GFX6-8,10.3 */ SI_TRACKED_IA_MULTI_VGT_PARAM, /* GFX6-8 (GFX9+ can reuse this slot) */ SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, /* GFX9 - the slots above can be reused */ diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/si_state_binning.c mesa-24.0.5/src/gallium/drivers/radeonsi/si_state_binning.c --- mesa-24.0.3/src/gallium/drivers/radeonsi/si_state_binning.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/si_state_binning.c 2024-04-10 20:17:49.000000000 +0000 @@ -393,6 +393,9 @@ if (sctx->gfx_level >= GFX10) { struct uvec2 bin_size = {}; struct uvec2 bin_size_extend = {}; + unsigned binning_disabled = + sctx->gfx_level >= GFX11_5 ? V_028C44_BINNING_DISABLED + : V_028C44_DISABLE_BINNING_USE_NEW_SC; bin_size.x = 128; bin_size.y = sctx->framebuffer.min_bytes_per_pixel <= 4 ? 128 : 64; @@ -404,7 +407,7 @@ radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0, - S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) | + S_028C44_BINNING_MODE(binning_disabled) | S_028C44_BIN_SIZE_X(bin_size.x == 16) | S_028C44_BIN_SIZE_Y(bin_size.y == 16) | S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) | diff -Nru mesa-24.0.3/src/gallium/drivers/radeonsi/si_state_shaders.cpp mesa-24.0.5/src/gallium/drivers/radeonsi/si_state_shaders.cpp --- mesa-24.0.3/src/gallium/drivers/radeonsi/si_state_shaders.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/radeonsi/si_state_shaders.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -4345,6 +4345,15 @@ radeon_begin(cs); radeon_opt_set_context_reg(sctx, R_028B54_VGT_SHADER_STAGES_EN, SI_TRACKED_VGT_SHADER_STAGES_EN, sctx->vgt_shader_stages_en); + if (sctx->gfx_level == GFX10_3) { + /* Legacy Tess+GS should disable reuse to prevent hangs on GFX10.3. */ + bool has_legacy_tess_gs = G_028B54_HS_EN(sctx->vgt_shader_stages_en) && + G_028B54_GS_EN(sctx->vgt_shader_stages_en) && + !G_028B54_PRIMGEN_EN(sctx->vgt_shader_stages_en); /* !NGG */ + + radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF, + S_028AB4_REUSE_OFF(has_legacy_tess_gs)); + } radeon_end_update_context_roll(sctx); if (sctx->gfx_level >= GFX10) { diff -Nru mesa-24.0.3/src/gallium/drivers/svga/svga_draw.c mesa-24.0.5/src/gallium/drivers/svga/svga_draw.c --- mesa-24.0.3/src/gallium/drivers/svga/svga_draw.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/svga/svga_draw.c 2024-04-10 20:17:49.000000000 +0000 @@ -1006,6 +1006,7 @@ struct svga_context *svga = hwtnl->svga; struct svga_winsys_surface *indirect_handle; enum pipe_error ret; + bool is_instanced_draw = instance_count > 1 || start_instance > 0; assert(svga_have_vgpu10(svga)); assert(hwtnl->cmd.prim_count == 0); @@ -1096,7 +1097,7 @@ indirect_handle, indirect->offset); } - else if (instance_count > 1) { + else if (is_instanced_draw) { ret = SVGA3D_vgpu10_DrawIndexedInstanced(svga->swc, vcount, instance_count, @@ -1139,7 +1140,7 @@ indirect_handle, indirect->offset); } - else if (instance_count > 1) { + else if (is_instanced_draw) { ret = SVGA3D_vgpu10_DrawInstanced(svga->swc, vcount, instance_count, diff -Nru mesa-24.0.3/src/gallium/drivers/v3d/v3dx_draw.c mesa-24.0.5/src/gallium/drivers/v3d/v3dx_draw.c --- mesa-24.0.3/src/gallium/drivers/v3d/v3dx_draw.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/v3d/v3dx_draw.c 2024-04-10 20:17:49.000000000 +0000 @@ -709,6 +709,9 @@ } bool cs_loaded_any = false; + const bool cs_uses_builtins = v3d->prog.cs->prog_data.vs->uses_iid || + v3d->prog.cs->prog_data.vs->uses_biid || + v3d->prog.cs->prog_data.vs->uses_vid; for (int i = 0; i < vtx->num_elements; i++) { struct pipe_vertex_element *elem = &vtx->pipe[i]; struct pipe_vertex_buffer *vb = @@ -738,11 +741,18 @@ * inputs. (Since CS is just dead-code-elimination * compared to VS, we can't have CS loading but not * VS). + * + * GFXH-1602: first attribute must be active if using + * builtins. */ if (v3d->prog.cs->prog_data.vs->vattr_sizes[i]) cs_loaded_any = true; - if (i == vtx->num_elements - 1 && !cs_loaded_any) { + if (i == 0 && cs_uses_builtins && !cs_loaded_any) { attr.number_of_values_read_by_coordinate_shader = 1; + cs_loaded_any = true; + } else if (i == vtx->num_elements - 1 && !cs_loaded_any) { + attr.number_of_values_read_by_coordinate_shader = 1; + cs_loaded_any = true; } attr.maximum_index = 0xffffff; } diff -Nru mesa-24.0.3/src/gallium/drivers/zink/ci/traces-zink-restricted.yml mesa-24.0.5/src/gallium/drivers/zink/ci/traces-zink-restricted.yml --- mesa-24.0.3/src/gallium/drivers/zink/ci/traces-zink-restricted.yml 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/ci/traces-zink-restricted.yml 2024-04-10 20:17:49.000000000 +0000 @@ -60,7 +60,7 @@ text: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8986 TheRavenRemastered/Raven-f10900-v2.trace: gl-zink-anv-tgl: - checksum: db7b901177e7ac00cc489e0e13f71f76 + checksum: e910141d9520739c653fa7de0d8a1c9b TombRaider2013/TombRaider-f1430-v2.trace: gl-zink-anv-tgl: label: [crash] diff -Nru mesa-24.0.3/src/gallium/drivers/zink/ci/traces-zink.yml mesa-24.0.5/src/gallium/drivers/zink/ci/traces-zink.yml --- mesa-24.0.3/src/gallium/drivers/zink/ci/traces-zink.yml 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/ci/traces-zink.yml 2024-04-10 20:17:49.000000000 +0000 @@ -30,7 +30,7 @@ checksum: 433b69bea68cfe81914b857bbdc60ea5 gputest/pixmark-piano-v2.trace: gl-zink-anv-tgl: - checksum: 4c7afcce5d87ec2bced65e92a1c9a41c + checksum: 9e7b3f2d38e6cea705af8161cfd41465 gputest/triangle-v2.trace: gl-zink-anv-tgl: checksum: 5f694874b15bcd7a3689b387c143590b diff -Nru mesa-24.0.3/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt mesa-24.0.5/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt --- mesa-24.0.3/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt 2024-04-10 20:17:49.000000000 +0000 @@ -156,10 +156,6 @@ spec@!opengl 3.0@clearbuffer-depth-cs-probe,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index2,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-non-const-uniform-index,Fail - spec@arb_framebuffer_object@fbo-blit-scaled-linear,Fail @@ -530,10 +526,6 @@ spec@arb_shader_image_load_store@early-z,Fail spec@arb_shader_image_load_store@early-z@occlusion query test/early-z pass,Fail -spec@arb_shader_image_load_store@host-mem-barrier,Fail -spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/16x16,Fail -spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/4x4,Fail -spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/64x64,Fail spec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,Fail diff -Nru mesa-24.0.3/src/gallium/drivers/zink/ci/zink-lvp-fails.txt mesa-24.0.5/src/gallium/drivers/zink/ci/zink-lvp-fails.txt --- mesa-24.0.3/src/gallium/drivers/zink/ci/zink-lvp-fails.txt 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/ci/zink-lvp-fails.txt 2024-04-10 20:17:49.000000000 +0000 @@ -143,10 +143,6 @@ spec@!opengl 1.0@rasterpos@glsl_vs_gs_linked,Fail spec@!opengl 1.0@rasterpos@glsl_vs_tes_linked,Fail - -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index2,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-non-const-uniform-index,Fail spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2-mat2,Fail spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2x3-mat2x3,Fail spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2x4-mat2x4,Fail diff -Nru mesa-24.0.3/src/gallium/drivers/zink/ci/zink-radv-navi10-fails.txt mesa-24.0.5/src/gallium/drivers/zink/ci/zink-radv-navi10-fails.txt --- mesa-24.0.3/src/gallium/drivers/zink/ci/zink-radv-navi10-fails.txt 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/ci/zink-radv-navi10-fails.txt 2024-04-10 20:17:49.000000000 +0000 @@ -13,13 +13,8 @@ # #6322 spec@arb_framebuffer_object@fbo-blit-scaled-linear,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index2,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-non-const-uniform-index,Fail spec@arb_bindless_texture@compiler@samplers@arith-bound-sampler-texture2d.frag,Crash -spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-query,Fail -spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-query@MS8,Fail spec@arb_gpu_shader_fp64@execution@arb_gpu_shader_fp64-tf-separate,Fail spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2-mat2,Fail spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2x3-mat2x3,Fail diff -Nru mesa-24.0.3/src/gallium/drivers/zink/ci/zink-radv-navi31-fails.txt mesa-24.0.5/src/gallium/drivers/zink/ci/zink-radv-navi31-fails.txt --- mesa-24.0.3/src/gallium/drivers/zink/ci/zink-radv-navi31-fails.txt 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/ci/zink-radv-navi31-fails.txt 2024-04-10 20:17:49.000000000 +0000 @@ -13,14 +13,8 @@ # #6322 spec@arb_framebuffer_object@fbo-blit-scaled-linear,Fail - -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index2,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-non-const-uniform-index,Fail spec@arb_bindless_texture@compiler@samplers@arith-bound-sampler-texture2d.frag,Crash -spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-query,Fail -spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-query@MS8,Fail spec@arb_gpu_shader_fp64@execution@arb_gpu_shader_fp64-tf-separate,Fail spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2-mat2,Fail spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2x3-mat2x3,Fail diff -Nru mesa-24.0.3/src/gallium/drivers/zink/ci/zink-radv-polaris10-fails.txt mesa-24.0.5/src/gallium/drivers/zink/ci/zink-radv-polaris10-fails.txt --- mesa-24.0.3/src/gallium/drivers/zink/ci/zink-radv-polaris10-fails.txt 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/ci/zink-radv-polaris10-fails.txt 2024-04-10 20:17:49.000000000 +0000 @@ -13,9 +13,6 @@ # #6322 spec@arb_framebuffer_object@fbo-blit-scaled-linear,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index2,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-non-const-uniform-index,Fail spec@arb_bindless_texture@compiler@samplers@arith-bound-sampler-texture2d.frag,Crash spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-query,Fail diff -Nru mesa-24.0.3/src/gallium/drivers/zink/ci/zink-radv-vangogh-fails.txt mesa-24.0.5/src/gallium/drivers/zink/ci/zink-radv-vangogh-fails.txt --- mesa-24.0.3/src/gallium/drivers/zink/ci/zink-radv-vangogh-fails.txt 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/ci/zink-radv-vangogh-fails.txt 2024-04-10 20:17:49.000000000 +0000 @@ -13,13 +13,8 @@ # #6322 spec@arb_framebuffer_object@fbo-blit-scaled-linear,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index2,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-mixed-const-non-const-uniform-index,Fail -spec@arb_arrays_of_arrays@execution@image_store@basic-imagestore-non-const-uniform-index,Fail spec@arb_bindless_texture@compiler@samplers@arith-bound-sampler-texture2d.frag,Crash -spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-query,Fail -spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-query@MS8,Fail spec@arb_gpu_shader_fp64@execution@arb_gpu_shader_fp64-tf-separate,Fail spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2-mat2,Fail spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2x3-mat2x3,Fail diff -Nru mesa-24.0.3/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c mesa-24.0.5/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c --- mesa-24.0.3/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c 2024-04-10 20:17:49.000000000 +0000 @@ -114,6 +114,7 @@ subgroup_size_var; SpvId discard_func; + SpvId float_array_type[2]; }; static SpvId @@ -2784,6 +2785,16 @@ nir_alu_type atype; nir_alu_type ret_type = nir_atomic_op_type(nir_intrinsic_atomic_op(intr)) == nir_type_float ? nir_type_float : nir_type_uint; SpvId ptr = get_src(ctx, &intr->src[0], &atype); + if (atype != ret_type && ret_type == nir_type_float) { + unsigned bit_size = nir_src_bit_size(intr->src[0]); + SpvId *float_array_type = &ctx->float_array_type[bit_size == 32 ? 0 : 1]; + if (!*float_array_type) { + *float_array_type = spirv_builder_type_pointer(&ctx->builder, SpvStorageClassStorageBuffer, + spirv_builder_type_float(&ctx->builder, bit_size)); + } + ptr = emit_unop(ctx, SpvOpBitcast, *float_array_type, ptr); + } + SpvId param = get_src(ctx, &intr->src[1], &atype); if (atype != ret_type) param = cast_src_to_type(ctx, param, intr->src[1], ret_type); @@ -3542,6 +3553,9 @@ tex->sampler_dim == GLSL_SAMPLER_DIM_2D || tex->sampler_dim == GLSL_SAMPLER_DIM_3D || tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE || + /* External images are interpreted as 2D in type_to_dim, + * so LOD is allowed */ + tex->sampler_dim == GLSL_SAMPLER_DIM_EXTERNAL || /* RECT will always become 2D, so this is fine */ tex->sampler_dim == GLSL_SAMPLER_DIM_RECT); } @@ -3974,8 +3988,11 @@ } SpvStorageClass storage_class = get_storage_class(var); - SpvId base, type; + SpvId type; nir_alu_type atype = nir_type_uint; + + SpvId base = get_src(ctx, &deref->parent, &atype); + switch (var->data.mode) { case nir_var_mem_ubo: @@ -4017,6 +4034,26 @@ if (itype == nir_type_float) index = emit_bitcast(ctx, get_uvec_type(ctx, 32, 1), index); + if (var->data.mode == nir_var_uniform || var->data.mode == nir_var_image) { + nir_deref_instr *aoa_deref = nir_src_as_deref(deref->parent); + uint32_t inner_stride = glsl_array_size(aoa_deref->type); + + while (aoa_deref->deref_type != nir_deref_type_var) { + assert(aoa_deref->deref_type == nir_deref_type_array); + + SpvId aoa_index = get_src(ctx, &aoa_deref->arr.index, &itype); + if (itype == nir_type_float) + aoa_index = emit_bitcast(ctx, get_uvec_type(ctx, 32, 1), aoa_index); + + aoa_deref = nir_src_as_deref(aoa_deref->parent); + + uint32_t stride = glsl_get_aoa_size(aoa_deref->type) / inner_stride; + aoa_index = emit_binop(ctx, SpvOpIMul, get_uvec_type(ctx, 32, 1), aoa_index, + emit_uint_const(ctx, 32, stride)); + index = emit_binop(ctx, SpvOpIAdd, get_uvec_type(ctx, 32, 1), index, aoa_index); + } + } + SpvId ptr_type = spirv_builder_type_pointer(&ctx->builder, storage_class, type); diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_batch.c mesa-24.0.5/src/gallium/drivers/zink/zink_batch.c --- mesa-24.0.3/src/gallium/drivers/zink/zink_batch.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_batch.c 2024-04-10 20:17:49.000000000 +0000 @@ -757,7 +757,7 @@ unsigned i = 0; VkSemaphore *sem = bs->signal_semaphores.data; - set_foreach_remove(&bs->dmabuf_exports, entry) { + set_foreach(&bs->dmabuf_exports, entry) { struct zink_resource *res = (void*)entry->key; for (; res; res = zink_resource(res->base.b.next)) zink_screen_import_dmabuf_semaphore(screen, res, sem[i++]); @@ -765,6 +765,7 @@ struct pipe_resource *pres = (void*)entry->key; pipe_resource_reference(&pres, NULL); } + _mesa_set_clear(&bs->dmabuf_exports, NULL); bs->usage.submit_count++; end: diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_compiler.c mesa-24.0.5/src/gallium/drivers/zink/zink_compiler.c --- mesa-24.0.3/src/gallium/drivers/zink/zink_compiler.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_compiler.c 2024-04-10 20:17:49.000000000 +0000 @@ -2671,13 +2671,11 @@ if (intr->def.bit_size == 64) num_components *= 2; nir_src *src_offset = nir_get_io_offset_src(intr); - if (nir_src_is_const(*src_offset)) { - unsigned slot_offset = nir_src_as_uint(*src_offset); - if (s.location + slot_offset != wc->slot) - return false; - } else if (s.location > wc->slot || s.location + s.num_slots <= wc->slot) { + if (!nir_src_is_const(*src_offset)) + return false; + unsigned slot_offset = nir_src_as_uint(*src_offset); + if (s.location + slot_offset != wc->slot) return false; - } uint32_t readmask = BITFIELD_MASK(intr->num_components) << c; if (intr->def.bit_size == 64) readmask |= readmask << (intr->num_components + c); @@ -3633,6 +3631,8 @@ bool is_interp = false; if (!filter_io_instr(intr, &is_load, &is_input, &is_interp)) return false; + bool is_special_io = (b->shader->info.stage == MESA_SHADER_VERTEX && is_input) || + (b->shader->info.stage == MESA_SHADER_FRAGMENT && !is_input); unsigned loc = nir_intrinsic_io_semantics(intr).location; nir_src *src_offset = nir_get_io_offset_src(intr); const unsigned slot_offset = src_offset && nir_src_is_const(*src_offset) ? nir_src_as_uint(*src_offset) : 0; @@ -3661,9 +3661,8 @@ bool is_struct = glsl_type_is_struct(glsl_without_array(type)); if (is_struct) size = get_slot_components(var, var->data.location + slot_offset, var->data.location); - else if ((var->data.mode == nir_var_shader_out && var->data.location < VARYING_SLOT_VAR0) || - (var->data.mode == nir_var_shader_in && var->data.location < (b->shader->info.stage == MESA_SHADER_VERTEX ? VERT_ATTRIB_GENERIC0 : VARYING_SLOT_VAR0))) - size = glsl_type_is_array(type) ? glsl_get_aoa_size(type) : glsl_get_vector_elements(type); + else if (!is_special_io && var->data.compact) + size = glsl_get_aoa_size(type); else size = glsl_get_vector_elements(glsl_without_array(type)); assert(size); @@ -4913,13 +4912,13 @@ else var->data.driver_location = var->data.location; } - return true; + continue; } /* i/o interface blocks are required to be EXACT matches between stages: * iterate over all locations and set locations incrementally */ unsigned slot = 0; - for (unsigned i = 0; i < VARYING_SLOT_MAX; i++) { + for (unsigned i = 0; i < VARYING_SLOT_TESS_MAX; i++) { if (nir_slot_is_sysval_output(i, MESA_SHADER_NONE)) continue; bool found = false; diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_context.c mesa-24.0.5/src/gallium/drivers/zink/zink_context.c --- mesa-24.0.3/src/gallium/drivers/zink/zink_context.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_context.c 2024-04-10 20:17:49.000000000 +0000 @@ -2907,10 +2907,11 @@ if (has_swapchain) { ASSERTED struct zink_resource *res = zink_resource(ctx->fb_state.cbufs[0]->texture); zink_render_fixup_swapchain(ctx); - assert(ctx->dynamic_fb.info.renderArea.extent.width <= res->base.b.width0); - assert(ctx->dynamic_fb.info.renderArea.extent.height <= res->base.b.height0); - assert(ctx->fb_state.width <= res->base.b.width0); - assert(ctx->fb_state.height <= res->base.b.height0); + /* clamp for late swapchain resize */ + if (res->base.b.width0 < ctx->dynamic_fb.info.renderArea.extent.width) + ctx->dynamic_fb.info.renderArea.extent.width = res->base.b.width0; + if (res->base.b.height0 < ctx->dynamic_fb.info.renderArea.extent.height) + ctx->dynamic_fb.info.renderArea.extent.height = res->base.b.height0; } if (ctx->fb_state.zsbuf && zsbuf_used) { struct zink_surface *surf = zink_csurface(ctx->fb_state.zsbuf); @@ -4146,7 +4147,7 @@ struct zink_context *ctx = zink_context(pctx); struct zink_resource *res = zink_resource(pres); if (res->obj->dt) { - if (zink_kopper_acquired(res->obj->dt, res->obj->dt_idx)) { + if (zink_kopper_acquired(res->obj->dt, res->obj->dt_idx) && (!ctx->clears_enabled || !res->fb_bind_count)) { zink_batch_no_rp_safe(ctx); zink_kopper_readback_update(ctx, res); zink_screen(ctx->base.screen)->image_barrier(ctx, res, VK_IMAGE_LAYOUT_PRESENT_SRC_KHR, 0, VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT); diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_descriptors.c mesa-24.0.5/src/gallium/drivers/zink/zink_descriptors.c --- mesa-24.0.3/src/gallium/drivers/zink/zink_descriptors.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_descriptors.c 2024-04-10 20:17:49.000000000 +0000 @@ -825,11 +825,14 @@ dpci.poolSizeCount = num_type_sizes; dpci.flags = flags; dpci.maxSets = MAX_LAZY_DESCRIPTORS; - VkResult result = VKSCR(CreateDescriptorPool)(screen->dev, &dpci, 0, &pool); - if (result != VK_SUCCESS) { - mesa_loge("ZINK: vkCreateDescriptorPool failed (%s)", vk_Result_to_str(result)); - return VK_NULL_HANDLE; - } + VkResult result; + VRAM_ALLOC_LOOP(result, + VKSCR(CreateDescriptorPool)(screen->dev, &dpci, 0, &pool), + if (result != VK_SUCCESS) { + mesa_loge("ZINK: vkCreateDescriptorPool failed (%s)", vk_Result_to_str(result)); + return VK_NULL_HANDLE; + } + ); return pool; } diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_pipeline.c mesa-24.0.5/src/gallium/drivers/zink/zink_pipeline.c --- mesa-24.0.3/src/gallium/drivers/zink/zink_pipeline.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_pipeline.c 2024-04-10 20:17:49.000000000 +0000 @@ -273,7 +273,7 @@ if (screen->info.have_EXT_color_write_enable) dynamicStateEnables[state_count++] = VK_DYNAMIC_STATE_COLOR_WRITE_ENABLE_EXT; - assert(state->rast_prim != MESA_PRIM_COUNT); + assert(state->rast_prim != MESA_PRIM_COUNT || zink_debug & ZINK_DEBUG_SHADERDB); VkPipelineRasterizationLineStateCreateInfoEXT rast_line_state; if (screen->info.have_EXT_line_rasterization && diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_program.c mesa-24.0.5/src/gallium/drivers/zink/zink_program.c --- mesa-24.0.3/src/gallium/drivers/zink/zink_program.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_program.c 2024-04-10 20:17:49.000000000 +0000 @@ -669,14 +669,15 @@ static void update_gfx_program_optimal(struct zink_context *ctx, struct zink_gfx_program *prog) { - const union zink_shader_key_optimal *optimal_key = (union zink_shader_key_optimal*)&prog->last_variant_hash; - if (ctx->gfx_pipeline_state.shader_keys_optimal.key.vs_bits != optimal_key->vs_bits) { + const union zink_shader_key_optimal *key = (union zink_shader_key_optimal*)&ctx->gfx_pipeline_state.optimal_key; + const union zink_shader_key_optimal *last_prog_key = (union zink_shader_key_optimal*)&prog->last_variant_hash; + if (key->vs_bits != last_prog_key->vs_bits) { assert(!prog->is_separable); bool changed = update_gfx_shader_module_optimal(ctx, prog, ctx->last_vertex_stage->info.stage); ctx->gfx_pipeline_state.modules_changed |= changed; } - const bool shadow_needs_shader_swizzle = optimal_key->fs.shadow_needs_shader_swizzle && (ctx->dirty_gfx_stages & BITFIELD_BIT(MESA_SHADER_FRAGMENT)); - if (ctx->gfx_pipeline_state.shader_keys_optimal.key.fs_bits != optimal_key->fs_bits || + const bool shadow_needs_shader_swizzle = last_prog_key->fs.shadow_needs_shader_swizzle && (ctx->dirty_gfx_stages & BITFIELD_BIT(MESA_SHADER_FRAGMENT)); + if (key->fs_bits != last_prog_key->fs_bits || /* always recheck shadow swizzles since they aren't directly part of the key */ unlikely(shadow_needs_shader_swizzle)) { assert(!prog->is_separable); @@ -688,7 +689,7 @@ } } if (prog->shaders[MESA_SHADER_TESS_CTRL] && prog->shaders[MESA_SHADER_TESS_CTRL]->non_fs.is_generated && - ctx->gfx_pipeline_state.shader_keys_optimal.key.tcs_bits != optimal_key->tcs_bits) { + key->tcs_bits != last_prog_key->tcs_bits) { assert(!prog->is_separable); bool changed = update_gfx_shader_module_optimal(ctx, prog, MESA_SHADER_TESS_CTRL); ctx->gfx_pipeline_state.modules_changed |= changed; @@ -724,12 +725,16 @@ ctx->gfx_pipeline_state.final_hash ^= ctx->curr_program->last_variant_hash; if (entry) { prog = (struct zink_gfx_program*)entry->data; - if (prog->is_separable && !(zink_debug & ZINK_DEBUG_NOOPT)) { + if (prog->is_separable) { /* shader variants can't be handled by separable programs: sync and compile */ - if (!ZINK_SHADER_KEY_OPTIMAL_IS_DEFAULT(ctx->gfx_pipeline_state.optimal_key)) + if (!ZINK_SHADER_KEY_OPTIMAL_IS_DEFAULT(ctx->gfx_pipeline_state.optimal_key) || + (prog->base.uses_shobj ? !zink_can_use_shader_objects(ctx) : !zink_can_use_pipeline_libs(ctx))) util_queue_fence_wait(&prog->base.cache_fence); /* If the optimized linked pipeline is done compiling, swap it into place. */ - if (util_queue_fence_is_signalled(&prog->base.cache_fence)) { + if (util_queue_fence_is_signalled(&prog->base.cache_fence) && + /* but only if needed for ZINK_DEBUG=noopt */ + (!(zink_debug & ZINK_DEBUG_NOOPT) || !ZINK_SHADER_KEY_OPTIMAL_IS_DEFAULT(ctx->gfx_pipeline_state.optimal_key) || + (prog->base.uses_shobj ? !zink_can_use_shader_objects(ctx) : !zink_can_use_pipeline_libs(ctx)))) { prog = replace_separable_prog(screen, entry, prog); } } @@ -754,19 +759,19 @@ /* remove old hash */ ctx->gfx_pipeline_state.optimal_key = zink_sanitize_optimal_key(ctx->gfx_stages, ctx->gfx_pipeline_state.shader_keys_optimal.key.val); ctx->gfx_pipeline_state.final_hash ^= ctx->curr_program->last_variant_hash; - if (ctx->curr_program->is_separable && !(zink_debug & ZINK_DEBUG_NOOPT)) { + if (ctx->curr_program->is_separable && !ZINK_SHADER_KEY_OPTIMAL_IS_DEFAULT(ctx->gfx_pipeline_state.optimal_key) && + (ctx->curr_program->base.uses_shobj ? !zink_can_use_shader_objects(ctx) : !zink_can_use_pipeline_libs(ctx))) { struct zink_gfx_program *prog = ctx->curr_program; - if (!ZINK_SHADER_KEY_OPTIMAL_IS_DEFAULT(ctx->gfx_pipeline_state.optimal_key)) { - util_queue_fence_wait(&prog->base.cache_fence); - /* shader variants can't be handled by separable programs: sync and compile */ - perf_debug(ctx, "zink[gfx_compile]: non-default shader variant required with separate shader object program\n"); - struct hash_table *ht = &ctx->program_cache[zink_program_cache_stages(ctx->shader_stages)]; - const uint32_t hash = ctx->gfx_hash; - simple_mtx_lock(&ctx->program_lock[zink_program_cache_stages(ctx->shader_stages)]); - struct hash_entry *entry = _mesa_hash_table_search_pre_hashed(ht, hash, ctx->gfx_stages); - ctx->curr_program = replace_separable_prog(screen, entry, prog); - simple_mtx_unlock(&ctx->program_lock[zink_program_cache_stages(ctx->shader_stages)]); - } + + util_queue_fence_wait(&prog->base.cache_fence); + /* shader variants can't be handled by separable programs: sync and compile */ + perf_debug(ctx, "zink[gfx_compile]: non-default shader variant required with separate shader object program\n"); + struct hash_table *ht = &ctx->program_cache[zink_program_cache_stages(ctx->shader_stages)]; + const uint32_t hash = ctx->gfx_hash; + simple_mtx_lock(&ctx->program_lock[zink_program_cache_stages(ctx->shader_stages)]); + struct hash_entry *entry = _mesa_hash_table_search_pre_hashed(ht, hash, ctx->gfx_stages); + ctx->curr_program = replace_separable_prog(screen, entry, prog); + simple_mtx_unlock(&ctx->program_lock[zink_program_cache_stages(ctx->shader_stages)]); } update_gfx_program_optimal(ctx, ctx->curr_program); /* apply new hash */ diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_program.h mesa-24.0.5/src/gallium/drivers/zink/zink_program.h --- mesa-24.0.3/src/gallium/drivers/zink/zink_program.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_program.h 2024-04-10 20:17:49.000000000 +0000 @@ -418,6 +418,21 @@ !ctx->is_generated_gs_bound; } +/* stricter requirements */ +ALWAYS_INLINE static bool +zink_can_use_shader_objects(const struct zink_context *ctx) +{ + return + /* TODO: if there's ever a dynamic render extension with input attachments */ + !ctx->gfx_pipeline_state.render_pass && + ZINK_SHADER_KEY_OPTIMAL_IS_DEFAULT(ctx->gfx_pipeline_state.optimal_key) && + /* TODO: is sample shading even possible to handle with GPL? */ + !ctx->gfx_stages[MESA_SHADER_FRAGMENT]->info.fs.uses_sample_shading && + !ctx->gfx_pipeline_state.force_persample_interp && + !ctx->gfx_pipeline_state.min_samples && + !ctx->is_generated_gs_bound; +} + bool zink_set_rasterizer_discard(struct zink_context *ctx, bool disable); void diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_program_state.hpp mesa-24.0.5/src/gallium/drivers/zink/zink_program_state.hpp --- mesa-24.0.3/src/gallium/drivers/zink/zink_program_state.hpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_program_state.hpp 2024-04-10 20:17:49.000000000 +0000 @@ -168,7 +168,7 @@ !prog->inline_variants && likely(prog->last_pipeline[rp_idx][idx]) && /* this data is too big to compare in the fast-path */ likely(!prog->shaders[MESA_SHADER_FRAGMENT]->fs.legacy_shadow_mask)) { - state->pipeline = prog->last_pipeline[rp_idx][idx]; + state->pipeline = prog->last_pipeline[rp_idx][idx]->pipeline; return state->pipeline; } } @@ -245,7 +245,7 @@ /* update states for fastpath */ if (DYNAMIC_STATE >= ZINK_DYNAMIC_VERTEX_INPUT) { prog->last_finalized_hash[rp_idx][idx] = state->final_hash; - prog->last_pipeline[rp_idx][idx] = cache_entry->pipeline; + prog->last_pipeline[rp_idx][idx] = cache_entry; } return state->pipeline; } diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_resource.c mesa-24.0.5/src/gallium/drivers/zink/zink_resource.c --- mesa-24.0.3/src/gallium/drivers/zink/zink_resource.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_resource.c 2024-04-10 20:17:49.000000000 +0000 @@ -669,7 +669,7 @@ } if (want_cube) { ici->flags |= VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT; - if (get_image_usage(screen, ici, templ, bind, modifiers_count, modifiers, &mod) != ici->usage) + if ((get_image_usage(screen, ici, templ, bind, modifiers_count, modifiers, &mod) & ici->usage) != ici->usage) ici->flags &= ~VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT; } diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_screen.c mesa-24.0.5/src/gallium/drivers/zink/zink_screen.c --- mesa-24.0.3/src/gallium/drivers/zink/zink_screen.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_screen.c 2024-04-10 20:17:49.000000000 +0000 @@ -1466,12 +1466,6 @@ zink_destroy_screen(struct pipe_screen *pscreen) { struct zink_screen *screen = zink_screen(pscreen); - struct zink_batch_state *bs = screen->free_batch_states; - while (bs) { - struct zink_batch_state *bs_next = bs->next; - zink_batch_state_destroy(screen, bs); - bs = bs_next; - } #ifdef HAVE_RENDERDOC_APP_H if (screen->renderdoc_capture_all && p_atomic_dec_zero(&num_screens)) @@ -1484,6 +1478,13 @@ if (screen->copy_context) screen->copy_context->base.destroy(&screen->copy_context->base); + struct zink_batch_state *bs = screen->free_batch_states; + while (bs) { + struct zink_batch_state *bs_next = bs->next; + zink_batch_state_destroy(screen, bs); + bs = bs_next; + } + if (VK_NULL_HANDLE != screen->debugUtilsCallbackHandle) { VKSCR(DestroyDebugUtilsMessengerEXT)(screen->instance, screen->debugUtilsCallbackHandle, NULL); } @@ -2551,9 +2552,11 @@ default: return 0; } - VkImageUsageFlags flags = VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT | - VK_IMAGE_USAGE_STORAGE_BIT | VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT; - flags |= is_zs ? VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT : VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT; + + VkImageUsageFlags use_flags = VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT | + VK_IMAGE_USAGE_STORAGE_BIT; + use_flags |= is_zs ? VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT : VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT; + VkImageUsageFlags flags = screen->format_props[pformat].optimalTilingFeatures & use_flags; VkSparseImageFormatProperties props[4]; //planar? unsigned prop_count = ARRAY_SIZE(props); VKSCR(GetPhysicalDeviceSparseImageFormatProperties)(screen->pdev, format, type, @@ -2562,11 +2565,21 @@ VK_IMAGE_TILING_OPTIMAL, &prop_count, props); if (!prop_count) { - if (pformat == PIPE_FORMAT_R9G9B9E5_FLOAT) { - screen->faked_e5sparse = true; - goto hack_it_up; + /* format may not support storage; try without */ + flags &= ~VK_IMAGE_USAGE_STORAGE_BIT; + prop_count = ARRAY_SIZE(props); + VKSCR(GetPhysicalDeviceSparseImageFormatProperties)(screen->pdev, format, type, + multi_sample ? VK_SAMPLE_COUNT_2_BIT : VK_SAMPLE_COUNT_1_BIT, + flags, + VK_IMAGE_TILING_OPTIMAL, + &prop_count, props); + if (!prop_count) { + if (pformat == PIPE_FORMAT_R9G9B9E5_FLOAT) { + screen->faked_e5sparse = true; + goto hack_it_up; + } + return 0; } - return 0; } if (size) { diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_synchronization.cpp mesa-24.0.5/src/gallium/drivers/zink/zink_synchronization.cpp --- mesa-24.0.3/src/gallium/drivers/zink/zink_synchronization.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_synchronization.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -673,6 +673,7 @@ } else { bmb.srcAccessMask = res->obj->access; } + bmb.dstAccessMask = flags; VKCTX(CmdPipelineBarrier)( cmdbuf, stages, diff -Nru mesa-24.0.3/src/gallium/drivers/zink/zink_types.h mesa-24.0.5/src/gallium/drivers/zink/zink_types.h --- mesa-24.0.3/src/gallium/drivers/zink/zink_types.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/drivers/zink/zink_types.h 2024-04-10 20:17:49.000000000 +0000 @@ -1137,7 +1137,7 @@ uint32_t last_variant_hash; uint32_t last_finalized_hash[2][4]; //[dynamic, renderpass][primtype idx] - VkPipeline last_pipeline[2][4]; //[dynamic, renderpass][primtype idx] + struct zink_gfx_pipeline_cache_entry *last_pipeline[2][4]; //[dynamic, renderpass][primtype idx] struct zink_gfx_lib_cache *libs; }; diff -Nru mesa-24.0.3/src/gallium/frontends/nine/device9.c mesa-24.0.5/src/gallium/frontends/nine/device9.c --- mesa-24.0.3/src/gallium/frontends/nine/device9.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/frontends/nine/device9.c 2024-04-10 20:17:49.000000000 +0000 @@ -1062,6 +1062,7 @@ /* XXX: better use GetBackBuffer here ? */ This->device_needs_reset = (hr != D3D_OK); + This->in_scene = FALSE; /* Not sure if should be done also for ResetEx */ return hr; } diff -Nru mesa-24.0.3/src/gallium/frontends/nine/iunknown.c mesa-24.0.5/src/gallium/frontends/nine/iunknown.c --- mesa-24.0.3/src/gallium/frontends/nine/iunknown.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/frontends/nine/iunknown.c 2024-04-10 20:17:49.000000000 +0000 @@ -48,6 +48,7 @@ This->forward = false; This->bind = 0; } + This->has_bind_or_refs = This->bind + This->refs; This->container = pParams->container; This->device = pParams->device; @@ -119,6 +120,7 @@ r = p_atomic_inc_return(&This->refs); if (r == 1) { + p_atomic_inc(&This->has_bind_or_refs); if (This->device) NineUnknown_AddRef(NineUnknown(This->device)); } @@ -142,9 +144,11 @@ if (r == 0) { struct NineDevice9 *device = This->device; + UINT b_or_ref = p_atomic_dec_return(&This->has_bind_or_refs); /* Containers (here with !forward) take care of item destruction */ - if (!This->container && This->bind == 0) { + if (!This->container && b_or_ref == 0) { + assert(p_atomic_read(&This->bind) == 0); This->dtor(This); } if (device) { @@ -166,8 +170,10 @@ if (r == 0) { struct NineDevice9 *device = This->device; + UINT b_or_ref = p_atomic_dec_return(&This->has_bind_or_refs); /* Containers (here with !forward) take care of item destruction */ - if (!This->container && This->bind == 0) { + if (!This->container && b_or_ref == 0) { + assert(p_atomic_read(&This->bind) == 0); NineLockGlobalMutex(); This->dtor(This); NineUnlockGlobalMutex(); diff -Nru mesa-24.0.3/src/gallium/frontends/nine/iunknown.h mesa-24.0.5/src/gallium/frontends/nine/iunknown.h --- mesa-24.0.3/src/gallium/frontends/nine/iunknown.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/frontends/nine/iunknown.h 2024-04-10 20:17:49.000000000 +0000 @@ -47,6 +47,7 @@ int32_t refs; /* external reference count */ int32_t bind; /* internal bind count */ + int32_t has_bind_or_refs; /* 0 if no ref, 1 if bind or ref, 2 if both */ bool forward; /* whether to forward references to the container */ /* container: for surfaces and volumes only. @@ -130,7 +131,7 @@ static inline void NineUnknown_Destroy( struct NineUnknown *This ) { - assert(!(This->refs | This->bind)); + assert(!(This->refs | This->bind) && !This->has_bind_or_refs); This->dtor(This); } @@ -140,6 +141,8 @@ UINT b = p_atomic_inc_return(&This->bind); assert(b); + if (b == 1) + p_atomic_inc(&This->has_bind_or_refs); if (b == 1 && This->forward) NineUnknown_Bind(This->container); @@ -150,10 +153,13 @@ NineUnknown_Unbind( struct NineUnknown *This ) { UINT b = p_atomic_dec_return(&This->bind); + UINT b_or_ref = 1; + if (b == 0) + b_or_ref = p_atomic_dec_return(&This->has_bind_or_refs); if (b == 0 && This->forward) NineUnknown_Unbind(This->container); - else if (b == 0 && This->refs == 0 && !This->container) + else if (b_or_ref == 0 && !This->container) This->dtor(This); return b; @@ -173,7 +179,7 @@ assert(This->container && !This->forward); This->container = NULL; - if (!(This->refs | This->bind)) + if (!(This->has_bind_or_refs)) This->dtor(This); } diff -Nru mesa-24.0.3/src/gallium/frontends/nine/nine_ff.c mesa-24.0.5/src/gallium/frontends/nine/nine_ff.c --- mesa-24.0.3/src/gallium/frontends/nine/nine_ff.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/frontends/nine/nine_ff.c 2024-04-10 20:17:49.000000000 +0000 @@ -1953,7 +1953,7 @@ dst[19].z = dst[25].z * mtl->Ambient.b + mtl->Emissive.b; } - if (!(context->changed.group & NINE_STATE_FF_LIGHTING)) + if (!(context->changed.group & NINE_STATE_FF_LIGHTING) && !IS_D3DTS_DIRTY(context, VIEW)) return; for (l = 0; l < context->ff.num_lights_active; ++l) { diff -Nru mesa-24.0.3/src/gallium/frontends/nine/nine_ff.h mesa-24.0.5/src/gallium/frontends/nine/nine_ff.h --- mesa-24.0.3/src/gallium/frontends/nine/nine_ff.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/frontends/nine/nine_ff.h 2024-04-10 20:17:49.000000000 +0000 @@ -83,20 +83,21 @@ for (s = 0; s < num_stages; ++s) { unsigned gen = (context->ff.tex_stage[s][D3DTSS_TEXCOORDINDEX] >> 16) + 1; unsigned dim = context->ff.tex_stage[s][D3DTSS_TEXTURETRANSFORMFLAGS] & 0x7; + unsigned idx = context->ff.tex_stage[s][D3DTSS_TEXCOORDINDEX] & 7; unsigned proj = !!(context->ff.tex_stage[s][D3DTSS_TEXTURETRANSFORMFLAGS] & D3DTTFF_PROJECTED); - if (!context->vs) { + if (!context->programmable_vs) { if (dim > 4) - dim = input_texture_coord[s]; + dim = input_texture_coord[idx]; if (!dim && gen == NINED3DTSS_TCI_PASSTHRU) - dim = input_texture_coord[s]; + dim = input_texture_coord[idx]; else if (!dim) dim = 4; if (dim == 1) /* NV behaviour */ proj = 0; - if (dim > input_texture_coord[s] && gen == NINED3DTSS_TCI_PASSTHRU) + if (dim > input_texture_coord[idx] && gen == NINED3DTSS_TCI_PASSTHRU) proj = 0; } else { dim = 4; diff -Nru mesa-24.0.3/src/gallium/frontends/rusticl/core/kernel.rs mesa-24.0.5/src/gallium/frontends/rusticl/core/kernel.rs --- mesa-24.0.3/src/gallium/frontends/rusticl/core/kernel.rs 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/frontends/rusticl/core/kernel.rs 2024-04-10 20:17:49.000000000 +0000 @@ -458,22 +458,8 @@ let mut args = KernelArg::from_spirv_nir(args, nir); let mut internal_args = Vec::new(); - let dv_opts = nir_remove_dead_variables_options { - can_remove_var: Some(can_remove_var), - can_remove_var_data: ptr::null_mut(), - }; - nir_pass!( - nir, - nir_remove_dead_variables, - nir_variable_mode::nir_var_uniform - | nir_variable_mode::nir_var_image - | nir_variable_mode::nir_var_mem_constant - | nir_variable_mode::nir_var_mem_shared - | nir_variable_mode::nir_var_function_temp, - &dv_opts, - ); - - // asign locations for inline samplers + // asign locations for inline samplers. + // IMPORTANT: this needs to happen before nir_remove_dead_variables. let mut last_loc = -1; for v in nir .variables_with_mode(nir_variable_mode::nir_var_uniform | nir_variable_mode::nir_var_image) @@ -501,6 +487,21 @@ } } + let dv_opts = nir_remove_dead_variables_options { + can_remove_var: Some(can_remove_var), + can_remove_var_data: ptr::null_mut(), + }; + nir_pass!( + nir, + nir_remove_dead_variables, + nir_variable_mode::nir_var_uniform + | nir_variable_mode::nir_var_image + | nir_variable_mode::nir_var_mem_constant + | nir_variable_mode::nir_var_mem_shared + | nir_variable_mode::nir_var_function_temp, + &dv_opts, + ); + nir_pass!(nir, nir_lower_readonly_images_to_tex, true); nir_pass!( nir, diff -Nru mesa-24.0.3/src/gallium/frontends/rusticl/core/platform.rs mesa-24.0.5/src/gallium/frontends/rusticl/core/platform.rs --- mesa-24.0.3/src/gallium/frontends/rusticl/core/platform.rs 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/frontends/rusticl/core/platform.rs 2024-04-10 20:17:49.000000000 +0000 @@ -7,6 +7,8 @@ use rusticl_opencl_gen::*; use std::env; +use std::ptr::addr_of; +use std::ptr::addr_of_mut; use std::sync::Arc; use std::sync::Once; @@ -71,7 +73,8 @@ }; fn load_env() { - let debug = unsafe { &mut PLATFORM_DBG }; + // SAFETY: no other references exist at this point + let debug = unsafe { &mut *addr_of_mut!(PLATFORM_DBG) }; if let Ok(debug_flags) = env::var("RUSTICL_DEBUG") { for flag in debug_flags.split(',') { match flag { @@ -85,7 +88,8 @@ } } - let features = unsafe { &mut PLATFORM_FEATURES }; + // SAFETY: no other references exist at this point + let features = unsafe { &mut *addr_of_mut!(PLATFORM_FEATURES) }; if let Ok(feature_flags) = env::var("RUSTICL_FEATURES") { for flag in feature_flags.split(',') { match flag { @@ -106,17 +110,17 @@ pub fn get() -> &'static Self { debug_assert!(PLATFORM_ONCE.is_completed()); // SAFETY: no mut references exist at this point - unsafe { &PLATFORM } + unsafe { &*addr_of!(PLATFORM) } } pub fn dbg() -> &'static PlatformDebug { debug_assert!(PLATFORM_ENV_ONCE.is_completed()); - unsafe { &PLATFORM_DBG } + unsafe { &*addr_of!(PLATFORM_DBG) } } pub fn features() -> &'static PlatformFeatures { debug_assert!(PLATFORM_ENV_ONCE.is_completed()); - unsafe { &PLATFORM_FEATURES } + unsafe { &*addr_of!(PLATFORM_FEATURES) } } fn init(&mut self) { diff -Nru mesa-24.0.3/src/gallium/frontends/rusticl/core/program.rs mesa-24.0.5/src/gallium/frontends/rusticl/core/program.rs --- mesa-24.0.3/src/gallium/frontends/rusticl/core/program.rs 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/frontends/rusticl/core/program.rs 2024-04-10 20:17:49.000000000 +0000 @@ -20,6 +20,7 @@ use std::ffi::CString; use std::mem::size_of; use std::ptr; +use std::ptr::addr_of; use std::slice; use std::sync::Arc; use std::sync::Mutex; @@ -55,7 +56,7 @@ DISK_CACHE_ONCE.call_once(|| { DISK_CACHE = DiskCache::new("rusticl", &func_ptrs, 0); }); - &DISK_CACHE + &*addr_of!(DISK_CACHE) } } diff -Nru mesa-24.0.3/src/gallium/frontends/va/surface.c mesa-24.0.5/src/gallium/frontends/va/surface.c --- mesa-24.0.3/src/gallium/frontends/va/surface.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/frontends/va/surface.c 2024-04-10 20:17:49.000000000 +0000 @@ -713,6 +713,16 @@ config->profile, config->entrypoint, PIPE_VIDEO_CAP_MAX_HEIGHT); i++; +#if VA_CHECK_VERSION(1, 21, 0) + attribs[i].type = VASurfaceAttribAlignmentSize; + attribs[i].value.type = VAGenericValueTypeInteger; + attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE; + attribs[i].value.value.i = + pscreen->get_video_param(pscreen, + config->profile, config->entrypoint, + PIPE_VIDEO_CAP_ENC_SURFACE_ALIGNMENT); + i++; +#endif } else { attribs[i].type = VASurfaceAttribMaxWidth; attribs[i].value.type = VAGenericValueTypeInteger; diff -Nru mesa-24.0.3/src/gallium/include/pipe/p_video_enums.h mesa-24.0.5/src/gallium/include/pipe/p_video_enums.h --- mesa-24.0.3/src/gallium/include/pipe/p_video_enums.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/include/pipe/p_video_enums.h 2024-04-10 20:17:49.000000000 +0000 @@ -161,6 +161,10 @@ * Encoding Region Of Interest feature */ PIPE_VIDEO_CAP_ENC_ROI = 49, + /* + * Encoding surface width/height alignment + */ + PIPE_VIDEO_CAP_ENC_SURFACE_ALIGNMENT = 50, }; enum pipe_video_h264_enc_dbk_filter_mode_flags diff -Nru mesa-24.0.3/src/gallium/include/pipe/p_video_state.h mesa-24.0.5/src/gallium/include/pipe/p_video_state.h --- mesa-24.0.3/src/gallium/include/pipe/p_video_state.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/include/pipe/p_video_state.h 2024-04-10 20:17:49.000000000 +0000 @@ -2008,6 +2008,21 @@ uint32_t value; }; +union pipe_enc_cap_surface_alignment { + struct { + /** + * log2_width_alignment + */ + uint32_t log2_width_alignment : 4; + /** + * log2_height_alignment + */ + uint32_t log2_height_alignment : 4; + uint32_t reserved : 24; + } bits; + uint32_t value; +}; + #ifdef __cplusplus } #endif diff -Nru mesa-24.0.3/src/gallium/winsys/radeon/drm/radeon_drm_bo.c mesa-24.0.5/src/gallium/winsys/radeon/drm/radeon_drm_bo.c --- mesa-24.0.3/src/gallium/winsys/radeon/drm/radeon_drm_bo.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/gallium/winsys/radeon/drm/radeon_drm_bo.c 2024-04-10 20:17:49.000000000 +0000 @@ -729,7 +729,7 @@ { struct radeon_bo *bo = container_of(entry, struct radeon_bo, u.slab.entry); - return radeon_bo_can_reclaim(NULL, &bo->base); + return radeon_bo_can_reclaim(priv, &bo->base); } static void radeon_bo_slab_destroy(void *winsys, struct pb_buffer_lean *_buf) diff -Nru mesa-24.0.3/src/glx/drisw_glx.c mesa-24.0.5/src/glx/drisw_glx.c --- mesa-24.0.3/src/glx/drisw_glx.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/glx/drisw_glx.c 2024-04-10 20:17:49.000000000 +0000 @@ -1001,7 +1001,9 @@ if (!psc->has_multibuffer && !debug_get_bool_option("LIBGL_ALWAYS_SOFTWARE", false) && !debug_get_bool_option("LIBGL_KOPPER_DRI2", false)) { - CriticalErrorMessageF("DRI3 not available\n"); + /* only print error if zink was explicitly requested */ + if (pdpyp->zink == TRY_ZINK_YES) + CriticalErrorMessageF("DRI3 not available\n"); goto handle_error; } } @@ -1049,7 +1051,8 @@ glx_screen_cleanup(&psc->base); free(psc); - CriticalErrorMessageF("failed to load driver: %s\n", driver); + if (pdpyp->zink == TRY_ZINK_YES) + CriticalErrorMessageF("failed to load driver: %s\n", driver); return NULL; } @@ -1079,7 +1082,7 @@ * display pointer. */ _X_HIDDEN __GLXDRIdisplay * -driswCreateDisplay(Display * dpy, bool zink) +driswCreateDisplay(Display * dpy, enum try_zink zink) { struct drisw_display *pdpyp; diff -Nru mesa-24.0.3/src/glx/drisw_priv.h mesa-24.0.5/src/glx/drisw_priv.h --- mesa-24.0.3/src/glx/drisw_priv.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/glx/drisw_priv.h 2024-04-10 20:17:49.000000000 +0000 @@ -33,7 +33,7 @@ struct drisw_display { __GLXDRIdisplay base; - bool zink; + enum try_zink zink; }; struct drisw_screen diff -Nru mesa-24.0.3/src/glx/glxclient.h mesa-24.0.5/src/glx/glxclient.h --- mesa-24.0.3/src/glx/glxclient.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/glx/glxclient.h 2024-04-10 20:17:49.000000000 +0000 @@ -131,11 +131,17 @@ int refcount; }; +enum try_zink { + TRY_ZINK_NO, + TRY_ZINK_INFER, + TRY_ZINK_YES, +}; + /* ** Function to create and DRI display data and initialize the display ** dependent methods. */ -extern __GLXDRIdisplay *driswCreateDisplay(Display * dpy, bool zink); +extern __GLXDRIdisplay *driswCreateDisplay(Display * dpy, enum try_zink zink); extern __GLXDRIdisplay *dri2CreateDisplay(Display * dpy); extern __GLXDRIdisplay *dri3_create_display(Display * dpy); extern __GLXDRIdisplay *driwindowsCreateDisplay(Display * dpy); diff -Nru mesa-24.0.3/src/glx/glxext.c mesa-24.0.5/src/glx/glxext.c --- mesa-24.0.3/src/glx/glxext.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/glx/glxext.c 2024-04-10 20:17:49.000000000 +0000 @@ -914,7 +914,8 @@ } #endif /* GLX_USE_DRM */ if (glx_direct) - dpyPriv->driswDisplay = driswCreateDisplay(dpy, zink | try_zink); + dpyPriv->driswDisplay = driswCreateDisplay(dpy, zink ? TRY_ZINK_YES : + try_zink ? TRY_ZINK_INFER : TRY_ZINK_NO); #ifdef GLX_USE_WINDOWSGL if (glx_direct && glx_accel) @@ -935,7 +936,7 @@ if (try_zink) { free(dpyPriv->screens); dpyPriv->driswDisplay->destroyDisplay(dpyPriv->driswDisplay); - dpyPriv->driswDisplay = driswCreateDisplay(dpy, false); + dpyPriv->driswDisplay = driswCreateDisplay(dpy, TRY_ZINK_NO); fail = !AllocAndFetchScreenConfigs(dpy, dpyPriv, False); } #endif diff -Nru mesa-24.0.3/src/intel/blorp/blorp_genX_exec.h mesa-24.0.5/src/intel/blorp/blorp_genX_exec.h --- mesa-24.0.3/src/intel/blorp/blorp_genX_exec.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/blorp/blorp_genX_exec.h 2024-04-10 20:17:49.000000000 +0000 @@ -308,6 +308,8 @@ }; void *data = blorp_alloc_vertex_buffer(batch, sizeof(vertices), addr); + if (data == NULL) + return; memcpy(data, vertices, sizeof(vertices)); *size = sizeof(vertices); blorp_flush_range(batch, data, *size); @@ -329,6 +331,8 @@ const uint32_t *const inputs_src = (const uint32_t *)¶ms->wm_inputs; void *data = blorp_alloc_vertex_buffer(batch, *size, addr); + if (data == NULL) + return; uint32_t *inputs = data; /* Copy in the VS inputs */ @@ -424,8 +428,10 @@ const uint32_t num_vbs = ARRAY_SIZE(vb); struct blorp_address addrs[2] = {}; - uint32_t sizes[2]; + uint32_t sizes[2] = {}; blorp_emit_vertex_data(batch, params, &addrs[0], &sizes[0]); + if (sizes[0] == 0) + return; blorp_fill_vertex_buffer_state(vb, 0, addrs[0], sizes[0], 3 * sizeof(float)); @@ -1147,6 +1153,8 @@ int size = GENX(BLEND_STATE_length) * 4; size += GENX(BLEND_STATE_ENTRY_length) * 4 * params->num_draw_buffers; uint32_t *state = blorp_alloc_dynamic_state(batch, size, 64, &offset); + if (state == NULL) + return 0; uint32_t *pos = state; GENX(BLEND_STATE_pack)(NULL, pos, &blend); @@ -2103,6 +2111,11 @@ &push_const_offset) : blorp_alloc_dynamic_state(batch, push_const_size, 64, &push_const_offset); + if (push_const == NULL) { + *state_offset = 0; + *state_size = 0; + return; + } memset(push_const, 0x0, push_const_size); void *dst = push_const; @@ -2281,6 +2294,8 @@ uint32_t idd_offset; uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t); void *state = blorp_alloc_dynamic_state(batch, size, 64, &idd_offset); + if (state == NULL) + return; GENX(INTERFACE_DESCRIPTOR_DATA_pack)(NULL, state, &idd); blorp_emit(batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) { diff -Nru mesa-24.0.3/src/intel/compiler/brw_disasm.c mesa-24.0.5/src/intel/compiler/brw_disasm.c --- mesa-24.0.3/src/intel/compiler/brw_disasm.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/compiler/brw_disasm.c 2024-04-10 20:17:49.000000000 +0000 @@ -1560,7 +1560,10 @@ if (subreg_nr) format(file, ".%d", subreg_nr); - src_align1_region(file, 1, 1, 0); + src_align1_region(file, + BRW_VERTICAL_STRIDE_1, + BRW_WIDTH_1, + BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0); string(file, brw_reg_type_to_letters(type)); @@ -1581,7 +1584,10 @@ if (subreg_nr) format(file, ".%d", subreg_nr); - src_align1_region(file, 1, 1, 0); + src_align1_region(file, + BRW_VERTICAL_STRIDE_1, + BRW_WIDTH_1, + BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0); string(file, brw_reg_type_to_letters(type)); @@ -1602,7 +1608,10 @@ if (subreg_nr) format(file, ".%d", subreg_nr); - src_align1_region(file, 1, 1, 0); + src_align1_region(file, + BRW_VERTICAL_STRIDE_1, + BRW_WIDTH_1, + BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0); string(file, brw_reg_type_to_letters(type)); diff -Nru mesa-24.0.3/src/intel/compiler/brw_eu_emit.c mesa-24.0.5/src/intel/compiler/brw_eu_emit.c --- mesa-24.0.3/src/intel/compiler/brw_eu_emit.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/compiler/brw_eu_emit.c 2024-04-10 20:17:49.000000000 +0000 @@ -121,7 +121,7 @@ dest.vstride == dest.width + 1)); assert(!dest.negate && !dest.abs); brw_inst_set_dst_reg_file(devinfo, inst, dest.file); - brw_inst_set_dst_da_reg_nr(devinfo, inst, dest.nr); + brw_inst_set_dst_da_reg_nr(devinfo, inst, phys_nr(devinfo, dest)); } else if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS || brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC) { @@ -141,10 +141,10 @@ brw_inst_set_dst_address_mode(devinfo, inst, dest.address_mode); if (dest.address_mode == BRW_ADDRESS_DIRECT) { - brw_inst_set_dst_da_reg_nr(devinfo, inst, dest.nr); + brw_inst_set_dst_da_reg_nr(devinfo, inst, phys_nr(devinfo, dest)); if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - brw_inst_set_dst_da1_subreg_nr(devinfo, inst, dest.subnr); + brw_inst_set_dst_da1_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest)); if (dest.hstride == BRW_HORIZONTAL_STRIDE_0) dest.hstride = BRW_HORIZONTAL_STRIDE_1; brw_inst_set_dst_hstride(devinfo, inst, dest.hstride); @@ -162,7 +162,7 @@ brw_inst_set_dst_hstride(devinfo, inst, 1); } } else { - brw_inst_set_dst_ia_subreg_nr(devinfo, inst, dest.subnr); + brw_inst_set_dst_ia_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest)); /* These are different sizes in align1 vs align16: */ @@ -242,7 +242,7 @@ reg.vstride == reg.width + 1)); assert(!reg.negate && !reg.abs); brw_inst_set_send_src0_reg_file(devinfo, inst, reg.file); - brw_inst_set_src0_da_reg_nr(devinfo, inst, reg.nr); + brw_inst_set_src0_da_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); } else if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS || brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC) { @@ -279,14 +279,14 @@ } } else { if (reg.address_mode == BRW_ADDRESS_DIRECT) { - brw_inst_set_src0_da_reg_nr(devinfo, inst, reg.nr); + brw_inst_set_src0_da_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - brw_inst_set_src0_da1_subreg_nr(devinfo, inst, reg.subnr); + brw_inst_set_src0_da1_subreg_nr(devinfo, inst, phys_subnr(devinfo, reg)); } else { brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16); } } else { - brw_inst_set_src0_ia_subreg_nr(devinfo, inst, reg.subnr); + brw_inst_set_src0_ia_subreg_nr(devinfo, inst, phys_subnr(devinfo, reg)); if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { brw_inst_set_src0_ia1_addr_imm(devinfo, inst, reg.indirect_offset); @@ -362,7 +362,7 @@ (reg.hstride == BRW_HORIZONTAL_STRIDE_1 && reg.vstride == reg.width + 1)); assert(!reg.negate && !reg.abs); - brw_inst_set_send_src1_reg_nr(devinfo, inst, reg.nr); + brw_inst_set_send_src1_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); brw_inst_set_send_src1_reg_file(devinfo, inst, reg.file); } else { /* From the IVB PRM Vol. 4, Pt. 3, Section 3.3.3.5: @@ -395,9 +395,9 @@ assert (reg.address_mode == BRW_ADDRESS_DIRECT); /* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */ - brw_inst_set_src1_da_reg_nr(devinfo, inst, reg.nr); + brw_inst_set_src1_da_reg_nr(devinfo, inst, phys_nr(devinfo, reg)); if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { - brw_inst_set_src1_da1_subreg_nr(devinfo, inst, reg.subnr); + brw_inst_set_src1_da1_subreg_nr(devinfo, inst, phys_subnr(devinfo, reg)); } else { brw_inst_set_src1_da16_subreg_nr(devinfo, inst, reg.subnr / 16); } @@ -832,7 +832,7 @@ if (devinfo->ver >= 12) { brw_inst_set_3src_a1_dst_reg_file(devinfo, inst, dest.file); - brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr); + brw_inst_set_3src_dst_reg_nr(devinfo, inst, phys_nr(devinfo, dest)); } else { if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE) { brw_inst_set_3src_a1_dst_reg_file(devinfo, inst, @@ -844,7 +844,7 @@ brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr); } } - brw_inst_set_3src_a1_dst_subreg_nr(devinfo, inst, dest.subnr / 8); + brw_inst_set_3src_a1_dst_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest) / 8); brw_inst_set_3src_a1_dst_hstride(devinfo, inst, BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1); @@ -868,11 +868,11 @@ devinfo, inst, to_3src_align1_vstride(devinfo, src0.vstride)); brw_inst_set_3src_a1_src0_hstride(devinfo, inst, to_3src_align1_hstride(src0.hstride)); - brw_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, src0.subnr); + brw_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, phys_subnr(devinfo, src0)); if (src0.type == BRW_REGISTER_TYPE_NF) { brw_inst_set_3src_src0_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR); } else { - brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr); + brw_inst_set_3src_src0_reg_nr(devinfo, inst, phys_nr(devinfo, src0)); } brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs); brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate); @@ -882,11 +882,11 @@ brw_inst_set_3src_a1_src1_hstride(devinfo, inst, to_3src_align1_hstride(src1.hstride)); - brw_inst_set_3src_a1_src1_subreg_nr(devinfo, inst, src1.subnr); + brw_inst_set_3src_a1_src1_subreg_nr(devinfo, inst, phys_subnr(devinfo, src1)); if (src1.file == BRW_ARCHITECTURE_REGISTER_FILE) { brw_inst_set_3src_src1_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR); } else { - brw_inst_set_3src_src1_reg_nr(devinfo, inst, src1.nr); + brw_inst_set_3src_src1_reg_nr(devinfo, inst, phys_nr(devinfo, src1)); } brw_inst_set_3src_src1_abs(devinfo, inst, src1.abs); brw_inst_set_3src_src1_negate(devinfo, inst, src1.negate); @@ -897,8 +897,8 @@ brw_inst_set_3src_a1_src2_hstride(devinfo, inst, to_3src_align1_hstride(src2.hstride)); /* no vstride on src2 */ - brw_inst_set_3src_a1_src2_subreg_nr(devinfo, inst, src2.subnr); - brw_inst_set_3src_src2_reg_nr(devinfo, inst, src2.nr); + brw_inst_set_3src_a1_src2_subreg_nr(devinfo, inst, phys_subnr(devinfo, src2)); + brw_inst_set_3src_src2_reg_nr(devinfo, inst, phys_nr(devinfo, src2)); brw_inst_set_3src_src2_abs(devinfo, inst, src2.abs); brw_inst_set_3src_src2_negate(devinfo, inst, src2.negate); } @@ -2923,7 +2923,7 @@ assert(ex_desc.nr == BRW_ARF_ADDRESS); assert((ex_desc.subnr & 0x3) == 0); brw_inst_set_send_sel_reg32_ex_desc(devinfo, send, 1); - brw_inst_set_send_ex_desc_ia_subreg_nr(devinfo, send, ex_desc.subnr >> 2); + brw_inst_set_send_ex_desc_ia_subreg_nr(devinfo, send, phys_subnr(devinfo, ex_desc) >> 2); } if (ex_bso) { diff -Nru mesa-24.0.3/src/intel/compiler/brw_fs.cpp mesa-24.0.5/src/intel/compiler/brw_fs.cpp --- mesa-24.0.3/src/intel/compiler/brw_fs.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/compiler/brw_fs.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -3049,11 +3049,10 @@ foreach_block_and_inst(block, fs_inst, send, cfg) { if (send->opcode != SHADER_OPCODE_SEND || - send->mlen <= reg_unit(devinfo) || send->ex_mlen > 0) + send->mlen <= reg_unit(devinfo) || send->ex_mlen > 0 || + send->src[2].file != VGRF) continue; - assert(send->src[2].file == VGRF); - /* Currently don't split sends that reuse a previously used payload. */ fs_inst *lp = (fs_inst *) send->prev; @@ -4473,7 +4472,8 @@ */ if (inst->exec_size == 8 && inst->src[0].type != BRW_REGISTER_TYPE_Q && inst->src[0].type != BRW_REGISTER_TYPE_UQ) { - fs_reg acc(ARF, BRW_ARF_ACCUMULATOR, inst->src[1].type); + fs_reg acc = retype(brw_acc_reg(inst->exec_size), + inst->src[1].type); ibld.MOV(acc, inst->src[1]); fs_inst *add = ibld.ADD(inst->dst, acc, inst->src[0]); @@ -7101,6 +7101,9 @@ payload_ = new fs_thread_payload(*this, source_depth_to_render_target, runtime_check_aads_emit); + if (nir->info.ray_queries > 0) + limit_dispatch_width(16, "SIMD32 not supported with ray queries.\n"); + if (do_rep_send) { assert(dispatch_width == 16); emit_repclear_shader(); @@ -7768,9 +7771,6 @@ " pixel shading.\n"); } - if (nir->info.ray_queries > 0 && v8) - v8->limit_dispatch_width(16, "SIMD32 with ray queries.\n"); - if (!has_spilled && (!v8 || v8->max_dispatch_width >= 16) && (INTEL_SIMD(FS, 16) || params->use_rep_send)) { diff -Nru mesa-24.0.3/src/intel/compiler/brw_fs_generator.cpp mesa-24.0.5/src/intel/compiler/brw_fs_generator.cpp --- mesa-24.0.3/src/intel/compiler/brw_fs_generator.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/compiler/brw_fs_generator.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -485,7 +485,7 @@ reg.nr = imm_byte_offset / REG_SIZE; reg.subnr = imm_byte_offset % REG_SIZE; - if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) { + if (type_sz(reg.type) > 4 && !devinfo->has_64bit_int) { brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0), subscript(reg, BRW_REGISTER_TYPE_D, 0)); brw_set_default_swsb(p, tgl_swsb_null()); @@ -567,7 +567,7 @@ if (type_sz(reg.type) > 4 && ((devinfo->verx10 == 70) || devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) || - !devinfo->has_64bit_float || devinfo->verx10 >= 125)) { + !devinfo->has_64bit_int)) { /* IVB has an issue (which we found empirically) where it reads two * address register components per channel for indirectly addressed * 64-bit sources. diff -Nru mesa-24.0.3/src/intel/compiler/brw_fs_lower_regioning.cpp mesa-24.0.5/src/intel/compiler/brw_fs_lower_regioning.cpp --- mesa-24.0.3/src/intel/compiler/brw_fs_lower_regioning.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/compiler/brw_fs_lower_regioning.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -190,18 +190,6 @@ else return brw_int_type(type_sz(t), false); - case SHADER_OPCODE_BROADCAST: - case SHADER_OPCODE_MOV_INDIRECT: - if (((devinfo->verx10 == 70 || - devinfo->platform == INTEL_PLATFORM_CHV || - intel_device_info_is_9lp(devinfo) || - devinfo->verx10 >= 125) && type_sz(inst->src[0].type) > 4) || - (devinfo->verx10 >= 125 && - brw_reg_type_is_floating_point(inst->src[0].type))) - return brw_int_type(type_sz(t), false); - else - return t; - default: return t; } @@ -572,6 +560,12 @@ ibld.at(block, inst->next).MOV(subscript(inst->dst, raw_type, j), subscript(tmp, raw_type, j)); + /* If the destination was an accumulator, after lowering it will be a + * GRF. Clear writes_accumulator for the instruction. + */ + if (inst->dst.is_accumulator()) + inst->writes_accumulator = false; + /* Point the original instruction at the temporary, making sure to keep * any destination modifiers in the instruction. */ diff -Nru mesa-24.0.3/src/intel/compiler/brw_fs_nir.cpp mesa-24.0.5/src/intel/compiler/brw_fs_nir.cpp --- mesa-24.0.3/src/intel/compiler/brw_fs_nir.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/compiler/brw_fs_nir.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -4608,7 +4608,7 @@ brw_type_for_nir_type(devinfo, nir_intrinsic_src_type(instr)); dest = retype(dest, dest_type); - fs_reg src2 = retype(get_nir_src(ntb, instr->src[2]), dest_type); + fs_reg src0 = retype(get_nir_src(ntb, instr->src[0]), dest_type); const fs_reg dest_hf = dest; fs_builder bld8 = bld.exec_all().group(8, 0); @@ -4624,24 +4624,24 @@ !s.compiler->lower_dpas) { dest = bld8.vgrf(BRW_REGISTER_TYPE_F, rcount); - if (src2.file != ARF) { - const fs_reg src2_hf = src2; + if (src0.file != ARF) { + const fs_reg src0_hf = src0; - src2 = bld8.vgrf(BRW_REGISTER_TYPE_F, rcount); + src0 = bld8.vgrf(BRW_REGISTER_TYPE_F, rcount); for (unsigned i = 0; i < 4; i++) { - bld16.MOV(byte_offset(src2, REG_SIZE * i * 2), - byte_offset(src2_hf, REG_SIZE * i)); + bld16.MOV(byte_offset(src0, REG_SIZE * i * 2), + byte_offset(src0_hf, REG_SIZE * i)); } } else { - src2 = retype(src2, BRW_REGISTER_TYPE_F); + src0 = retype(src0, BRW_REGISTER_TYPE_F); } } bld8.DPAS(dest, - src2, + src0, + retype(get_nir_src(ntb, instr->src[2]), src_type), retype(get_nir_src(ntb, instr->src[1]), src_type), - retype(get_nir_src(ntb, instr->src[0]), src_type), sdepth, rcount) ->saturate = nir_intrinsic_saturate(instr); diff -Nru mesa-24.0.3/src/intel/compiler/brw_fs_validate.cpp mesa-24.0.5/src/intel/compiler/brw_fs_validate.cpp --- mesa-24.0.3/src/intel/compiler/brw_fs_validate.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/compiler/brw_fs_validate.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -191,8 +191,8 @@ */ if (intel_needs_workaround(devinfo, 14014617373) && inst->dst.is_accumulator() && - inst->dst.offset == 0) { - fsv_assert_eq(inst->dst.stride, 1); + phys_subnr(devinfo, inst->dst.as_brw_reg()) == 0) { + fsv_assert_eq(inst->dst.hstride, 1); } } } diff -Nru mesa-24.0.3/src/intel/compiler/brw_lower_logical_sends.cpp mesa-24.0.5/src/intel/compiler/brw_lower_logical_sends.cpp --- mesa-24.0.3/src/intel/compiler/brw_lower_logical_sends.cpp 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/compiler/brw_lower_logical_sends.cpp 2024-04-10 20:17:49.000000000 +0000 @@ -1009,10 +1009,14 @@ /* Build the actual header */ const fs_builder ubld = bld.exec_all().group(8 * reg_unit(devinfo), 0); const fs_builder ubld1 = ubld.group(1, 0); - ubld.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + if (devinfo->ver >= 11) + ubld.MOV(header, brw_imm_ud(0)); + else + ubld.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); if (inst->offset) { ubld1.MOV(component(header, 2), brw_imm_ud(inst->offset)); - } else if (bld.shader->stage != MESA_SHADER_VERTEX && + } else if (devinfo->ver < 11 && + bld.shader->stage != MESA_SHADER_VERTEX && bld.shader->stage != MESA_SHADER_FRAGMENT) { /* The vertex and fragment stages have g0.2 set to 0, so * header0.2 is 0 when g0 is copied. Other stages may not, so we diff -Nru mesa-24.0.3/src/intel/compiler/brw_nir_lower_cooperative_matrix.c mesa-24.0.5/src/intel/compiler/brw_nir_lower_cooperative_matrix.c --- mesa-24.0.3/src/intel/compiler/brw_nir_lower_cooperative_matrix.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/compiler/brw_nir_lower_cooperative_matrix.c 2024-04-10 20:17:49.000000000 +0000 @@ -251,10 +251,22 @@ const unsigned packing_factor = get_packing_factor(*desc, slice->type); nir_deref_instr *pointer = nir_src_as_deref(intrin->src[ptr_src]); + const unsigned ptr_comp_width = glsl_get_bit_size(pointer->type); + const unsigned ptr_num_comps = glsl_get_vector_elements(pointer->type); + + /* The stride is given in number of elements of the pointed type, which + * doesn't necessarily match the matrix element type, so we need to adjust + * it considering it may be a vector and have a different bit-width. + */ + nir_def *stride = nir_udiv_imm(b, + nir_imul_imm(b, + intrin->src[2].ssa, + ptr_comp_width * ptr_num_comps), + glsl_base_type_get_bit_size(desc->element_type)); if ((nir_intrinsic_matrix_layout(intrin) == GLSL_MATRIX_LAYOUT_ROW_MAJOR) == (desc->use != GLSL_CMAT_USE_B)) { - nir_def *stride = nir_udiv_imm(b, intrin->src[2].ssa, packing_factor); + stride = nir_udiv_imm(b, stride, packing_factor); const struct glsl_type *element_type = glsl_scalar_type(glsl_get_base_type(slice->type)); @@ -304,8 +316,6 @@ } } } else { - nir_def *stride = intrin->src[2].ssa; - const struct glsl_type *element_type = glsl_scalar_type(desc->element_type); const unsigned element_bits = glsl_base_type_get_bit_size(desc->element_type); const unsigned element_stride = element_bits / 8; @@ -639,9 +649,9 @@ nir_def *result = nir_dpas_intel(b, packing_factor * glsl_base_type_get_bit_size(dst_desc.element_type), + nir_load_deref(b, accum_slice), nir_load_deref(b, A_slice), nir_load_deref(b, B_slice), - nir_load_deref(b, accum_slice), .dest_type = nir_get_nir_type_for_glsl_base_type(dst_desc.element_type), .src_type = nir_get_nir_type_for_glsl_base_type(src_desc.element_type), .saturate = nir_intrinsic_saturate(intrin), diff -Nru mesa-24.0.3/src/intel/compiler/brw_reg.h mesa-24.0.5/src/intel/compiler/brw_reg.h --- mesa-24.0.3/src/intel/compiler/brw_reg.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/compiler/brw_reg.h 2024-04-10 20:17:49.000000000 +0000 @@ -260,6 +260,39 @@ }; }; +static inline unsigned +phys_nr(const struct intel_device_info *devinfo, const struct brw_reg reg) +{ + if (devinfo->ver >= 20) { + if (reg.file == BRW_GENERAL_REGISTER_FILE) + return reg.nr / 2; + else if (reg.file == BRW_ARCHITECTURE_REGISTER_FILE && + reg.nr >= BRW_ARF_ACCUMULATOR && + reg.nr < BRW_ARF_FLAG) + return BRW_ARF_ACCUMULATOR + (reg.nr - BRW_ARF_ACCUMULATOR) / 2; + else + return reg.nr; + } else { + return reg.nr; + } +} + +static inline unsigned +phys_subnr(const struct intel_device_info *devinfo, const struct brw_reg reg) +{ + if (devinfo->ver >= 20) { + if (reg.file == BRW_GENERAL_REGISTER_FILE || + (reg.file == BRW_ARCHITECTURE_REGISTER_FILE && + reg.nr >= BRW_ARF_ACCUMULATOR && + reg.nr < BRW_ARF_FLAG)) + return (reg.nr & 1) * REG_SIZE + reg.subnr; + else + return reg.subnr; + } else { + return reg.subnr; + } +} + static inline bool brw_regs_equal(const struct brw_reg *a, const struct brw_reg *b) { diff -Nru mesa-24.0.3/src/intel/dev/intel_device_info.c mesa-24.0.5/src/intel/dev/intel_device_info.c --- mesa-24.0.3/src/intel/dev/intel_device_info.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/dev/intel_device_info.c 2024-04-10 20:17:49.000000000 +0000 @@ -1667,6 +1667,8 @@ break; case INTEL_KMD_TYPE_XE: ret = intel_device_info_xe_get_info_from_fd(fd, devinfo); + if (devinfo->verx10 < 200) + mesa_logw("Support for this platform is experimental with Xe KMD, bug reports may be ignored."); break; default: ret = false; diff -Nru mesa-24.0.3/src/intel/dev/intel_kmd.c mesa-24.0.5/src/intel/dev/intel_kmd.c --- mesa-24.0.3/src/intel/dev/intel_kmd.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/dev/intel_kmd.c 2024-04-10 20:17:49.000000000 +0000 @@ -37,10 +37,8 @@ if (strcmp(version->name, "i915") == 0) type = INTEL_KMD_TYPE_I915; -#ifdef INTEL_XE_KMD_SUPPORTED else if (strcmp(version->name, "xe") == 0) type = INTEL_KMD_TYPE_XE; -#endif drmFreeVersion(version); return type; diff -Nru mesa-24.0.3/src/intel/isl/isl_emit_depth_stencil.c mesa-24.0.5/src/intel/isl/isl_emit_depth_stencil.c --- mesa-24.0.3/src/intel/isl/isl_emit_depth_stencil.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/isl/isl_emit_depth_stencil.c 2024-04-10 20:17:49.000000000 +0000 @@ -200,6 +200,9 @@ db.ControlSurfaceEnable = db.DepthBufferCompressionEnable = isl_aux_usage_has_ccs(info->hiz_usage); #endif +#if GFX_VER >= 12 + db.NullPageCoherencyEnable = info->depth_surf->usage & ISL_SURF_USAGE_SPARSE_BIT; +#endif } #if GFX_VER == 5 || GFX_VER == 6 @@ -271,6 +274,9 @@ sb.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(info->stencil_surf) >> 2; #endif +#if GFX_VER >= 12 + sb.NullPageCoherencyEnable = info->stencil_surf->usage & ISL_SURF_USAGE_SPARSE_BIT; +#endif } else { #if GFX_VER >= 12 sb.SurfaceType = SURFTYPE_NULL; diff -Nru mesa-24.0.3/src/intel/vulkan/anv_allocator.c mesa-24.0.5/src/intel/vulkan/anv_allocator.c --- mesa-24.0.3/src/intel/vulkan/anv_allocator.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/vulkan/anv_allocator.c 2024-04-10 20:17:49.000000000 +0000 @@ -1029,6 +1029,9 @@ stream->block = anv_state_pool_alloc_no_vg(stream->state_pool, block_size, PAGE_SIZE); + if (stream->block.alloc_size == 0) + return ANV_STATE_NULL; + util_dynarray_append(&stream->all_blocks, struct anv_state, stream->block); VG(VALGRIND_MAKE_MEM_NOACCESS(stream->block.map, block_size)); diff -Nru mesa-24.0.3/src/intel/vulkan/anv_device.c mesa-24.0.5/src/intel/vulkan/anv_device.c --- mesa-24.0.3/src/intel/vulkan/anv_device.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/vulkan/anv_device.c 2024-04-10 20:17:49.000000000 +0000 @@ -944,9 +944,10 @@ p->maxMultiviewViewCount = 16; p->maxMultiviewInstanceIndex = UINT32_MAX / 16; /* Our protected implementation is a memory encryption mechanism, it - * doesn't page fault. + * shouldn't page fault, but it hangs the HW so in terms of user visibility + * it's similar to a fault. */ - p->protectedNoFault = true; + p->protectedNoFault = false; /* This value doesn't matter for us today as our per-stage descriptors are * the real limit. */ @@ -2239,7 +2240,7 @@ device->flush_astc_ldr_void_extent_denorms = device->has_astc_ldr && !device->emu_astc_ldr; } - device->disable_fcv = intel_device_info_is_mtl(&device->info) || + device->disable_fcv = device->info.verx10 >= 125 || instance->disable_fcv; result = anv_physical_device_init_heaps(device, fd); @@ -3707,8 +3708,7 @@ pthread_mutex_destroy(&device->mutex); fail_vmas: util_vma_heap_finish(&device->vma_trtt); - if (!device->physical->indirect_descriptors) - util_vma_heap_finish(&device->vma_samplers); + util_vma_heap_finish(&device->vma_samplers); util_vma_heap_finish(&device->vma_desc); util_vma_heap_finish(&device->vma_hi); util_vma_heap_finish(&device->vma_lo); @@ -3823,8 +3823,7 @@ anv_bo_cache_finish(&device->bo_cache); util_vma_heap_finish(&device->vma_trtt); - if (!device->physical->indirect_descriptors) - util_vma_heap_finish(&device->vma_samplers); + util_vma_heap_finish(&device->vma_samplers); util_vma_heap_finish(&device->vma_desc); util_vma_heap_finish(&device->vma_hi); util_vma_heap_finish(&device->vma_lo); @@ -4065,7 +4064,7 @@ if (mem->vk.alloc_flags & VK_MEMORY_ALLOCATE_DEVICE_ADDRESS_BIT) alloc_flags |= ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS; - if (mem->vk.alloc_flags & VK_MEMORY_PROPERTY_PROTECTED_BIT) + if (mem_type->propertyFlags & VK_MEMORY_PROPERTY_PROTECTED_BIT) alloc_flags |= ANV_BO_ALLOC_PROTECTED; /* For now, always allocated AUX-TT aligned memory, regardless of dedicated diff -Nru mesa-24.0.3/src/intel/vulkan/anv_formats.c mesa-24.0.5/src/intel/vulkan/anv_formats.c --- mesa-24.0.3/src/intel/vulkan/anv_formats.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/vulkan/anv_formats.c 2024-04-10 20:17:49.000000000 +0000 @@ -1464,6 +1464,10 @@ } } + if ((info->usage & VK_IMAGE_USAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR) && + !devinfo->has_coarse_pixel_primitive_and_cb) + goto unsupported; + /* From the bspec section entitled "Surface Layout and Tiling", * Gfx9 has a 256 GB limitation and Gfx11+ has a 16 TB limitation. */ diff -Nru mesa-24.0.3/src/intel/vulkan/anv_nir_apply_pipeline_layout.c mesa-24.0.5/src/intel/vulkan/anv_nir_apply_pipeline_layout.c --- mesa-24.0.3/src/intel/vulkan/anv_nir_apply_pipeline_layout.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/vulkan/anv_nir_apply_pipeline_layout.c 2024-04-10 20:17:49.000000000 +0000 @@ -594,8 +594,16 @@ } const uint32_t desc_bti = state->set[set].binding[binding].surface_offset; - assert(bind_layout->descriptor_surface_stride % 8 == 0); - const uint32_t desc_stride = bind_layout->descriptor_surface_stride / 8; + /* We don't care about the stride field for inline uniforms (see + * build_desc_addr_for_res_index), but for anything else we should be + * aligned to 8 bytes because we store a multiple of 8 in the packed info + * to be able to encode a stride up to 2040 (8 * 255). + */ + assert(bind_layout->type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK || + bind_layout->descriptor_surface_stride % 8 == 0); + const uint32_t desc_stride = + bind_layout->type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK ? 0 : + bind_layout->descriptor_surface_stride / 8; nir_def *packed = nir_ior_imm(b, diff -Nru mesa-24.0.3/src/intel/vulkan/genX_blorp_exec.c mesa-24.0.5/src/intel/vulkan/genX_blorp_exec.c --- mesa-24.0.3/src/intel/vulkan/genX_blorp_exec.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/vulkan/genX_blorp_exec.c 2024-04-10 20:17:49.000000000 +0000 @@ -417,7 +417,9 @@ blorp_exec(batch, params); + cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT; cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT; + cmd_buffer->state.compute.pipeline_dirty = true; } static void diff -Nru mesa-24.0.3/src/intel/vulkan/genX_cmd_buffer.c mesa-24.0.5/src/intel/vulkan/genX_cmd_buffer.c --- mesa-24.0.3/src/intel/vulkan/genX_cmd_buffer.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/vulkan/genX_cmd_buffer.c 2024-04-10 20:17:49.000000000 +0000 @@ -2928,6 +2928,16 @@ }; } + /* SKL PRMs, Volume 7: 3D-Media-GPGPU, Programming Restrictions for + * PIPE_CONTROL, Flush Types: + * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." + * For newer platforms this is documented in the PIPE_CONTROL instruction + * page. + */ + if (current_pipeline == GPGPU && + (bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT)) + bits |= ANV_PIPE_CS_STALL_BIT; + #if INTEL_NEEDS_WA_1409600907 /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must * be set with any PIPE_CONTROL with Depth Flush Enable bit set. @@ -3333,6 +3343,10 @@ const struct anv_graphics_pipeline *pipeline = anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline); + /* We cannot generate readable commands in protected mode. */ + if (cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT) + return false; + /* Limit generated draws to pipelines without HS stage. This makes things * simpler for implementing Wa_1306463417, Wa_16011107343. */ @@ -3343,6 +3357,33 @@ return count >= device->physical->instance->generated_indirect_threshold; } +static void +genX(cmd_buffer_set_protected_memory)(struct anv_cmd_buffer *cmd_buffer, + bool enabled) +{ +#if GFX_VER >= 12 + if (enabled) { + anv_batch_emit(&cmd_buffer->batch, GENX(MI_SET_APPID), appid) { + /* Default value for single session. */ + appid.ProtectedMemoryApplicationID = cmd_buffer->device->protected_session_id; + appid.ProtectedMemoryApplicationIDType = DISPLAY_APP; + } + } + anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { + pc.PipeControlFlushEnable = true; + pc.DCFlushEnable = true; + pc.RenderTargetCacheFlushEnable = true; + pc.CommandStreamerStallEnable = true; + if (enabled) + pc.ProtectedMemoryEnable = true; + else + pc.ProtectedMemoryDisable = true; + } +#else + unreachable("Protected content not supported"); +#endif +} + VkResult genX(BeginCommandBuffer)( VkCommandBuffer commandBuffer, @@ -3417,19 +3458,8 @@ #if GFX_VER >= 12 if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY && - cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT) { - anv_batch_emit(&cmd_buffer->batch, GENX(MI_SET_APPID), appid) { - /* Default value for single session. */ - appid.ProtectedMemoryApplicationID = cmd_buffer->device->protected_session_id; - appid.ProtectedMemoryApplicationIDType = DISPLAY_APP; - } - anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { - pc.CommandStreamerStallEnable = true; - pc.DCFlushEnable = true; - pc.RenderTargetCacheFlushEnable = true; - pc.ProtectedMemoryEnable = true; - } - } + cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT) + genX(cmd_buffer_set_protected_memory)(cmd_buffer, true); #endif genX(cmd_buffer_emit_state_base_address)(cmd_buffer); @@ -3643,14 +3673,8 @@ #if GFX_VER >= 12 if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY && - cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT) { - anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { - pc.CommandStreamerStallEnable = true; - pc.DCFlushEnable = true; - pc.RenderTargetCacheFlushEnable = true; - pc.ProtectedMemoryDisable = true; - } - } + cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT) + genX(cmd_buffer_set_protected_memory)(cmd_buffer, false); #endif trace_intel_end_cmd_buffer(&cmd_buffer->trace, cmd_buffer->vk.level); @@ -4072,6 +4096,7 @@ * tile cache flush to make sure any previous write is not going to * create WaW hazards. */ + pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT; pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT; break; case VK_ACCESS_2_SHADER_STORAGE_READ_BIT: diff -Nru mesa-24.0.3/src/intel/vulkan/genX_gfx_state.c mesa-24.0.5/src/intel/vulkan/genX_gfx_state.c --- mesa-24.0.3/src/intel/vulkan/genX_gfx_state.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/vulkan/genX_gfx_state.c 2024-04-10 20:17:49.000000000 +0000 @@ -1189,12 +1189,12 @@ * number of viewport programmed previously was larger than what we need * now, no need to reemit we can just keep the old programmed values. */ - if (BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_SF_CLIP) || + if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_SF_CLIP) || hw_state->vp_sf_clip.count < dyn->vp.viewport_count) { hw_state->vp_sf_clip.count = dyn->vp.viewport_count; BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_SF_CLIP); } - if (BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_CC) || + if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_CC) || hw_state->vp_cc.count < dyn->vp.viewport_count) { hw_state->vp_cc.count = dyn->vp.viewport_count; BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_CC); @@ -1260,7 +1260,7 @@ * number of viewport programmed previously was larger than what we need * now, no need to reemit we can just keep the old programmed values. */ - if (BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SCISSOR) || + if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_SCISSOR) || hw_state->scissor.count < dyn->vp.scissor_count) { hw_state->scissor.count = dyn->vp.scissor_count; BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SCISSOR); diff -Nru mesa-24.0.3/src/intel/vulkan/genX_init_state.c mesa-24.0.5/src/intel/vulkan/genX_init_state.c --- mesa-24.0.3/src/intel/vulkan/genX_init_state.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/vulkan/genX_init_state.c 2024-04-10 20:17:49.000000000 +0000 @@ -158,12 +158,15 @@ } /* TODO: Figure out FCV support for other platforms - * Testing indicates that FCV is broken on MTL, but works fine on DG2. - * Let's disable FCV on MTL for now till we figure out what's wrong. + * Testing indicates that FCV is broken gfx125. + * Let's disable FCV for now till we figure out what's wrong. * * Alternatively, it can be toggled off via drirc option 'anv_disable_fcv'. * * Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9987 + * Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10318 + * Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10795 + * Ref: Internal issue 1480 about Unreal Engine 5.1 */ anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) { mode.SliceHashingTableEnable = true; diff -Nru mesa-24.0.3/src/intel/vulkan/genX_video.c mesa-24.0.5/src/intel/vulkan/genX_video.c --- mesa-24.0.3/src/intel/vulkan/genX_video.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/vulkan/genX_video.c 2024-04-10 20:17:49.000000000 +0000 @@ -63,10 +63,46 @@ cmd_buffer->video.params = NULL; } +/* + * The default scan order of scaling lists is up-right-diagonal + * according to the spec. But the device requires raster order, + * so we need to convert from the passed scaling lists. + */ +static void +anv_h265_matrix_from_uprightdiagonal(StdVideoH265ScalingLists *out_sl, + const StdVideoH265ScalingLists *sl) +{ + uint8_t i, j; + + for (i = 0; i < 6; i++) { + for (j = 0; j < STD_VIDEO_H265_SCALING_LIST_4X4_NUM_ELEMENTS; j++) + out_sl->ScalingList4x4[i][vl_zscan_h265_up_right_diagonal_16[j]] = + sl->ScalingList4x4[i][j]; + + for (j = 0; j < STD_VIDEO_H265_SCALING_LIST_8X8_NUM_ELEMENTS; j++) + out_sl->ScalingList8x8[i][vl_zscan_h265_up_right_diagonal[j]] = + sl->ScalingList8x8[i][j]; + + for (j = 0; j < STD_VIDEO_H265_SCALING_LIST_16X16_NUM_ELEMENTS; j++) + out_sl->ScalingList16x16[i][vl_zscan_h265_up_right_diagonal[j]] = + sl->ScalingList16x16[i][j]; + } + + for (i = 0; i < STD_VIDEO_H265_SCALING_LIST_32X32_NUM_LISTS; i++) { + for (j = 0; j < STD_VIDEO_H265_SCALING_LIST_32X32_NUM_ELEMENTS; j++) + out_sl->ScalingList32x32[i][vl_zscan_h265_up_right_diagonal[j]] = + sl->ScalingList32x32[i][j]; + } +} + static void scaling_list(struct anv_cmd_buffer *cmd_buffer, const StdVideoH265ScalingLists *scaling_list) { + StdVideoH265ScalingLists out_sl = {0, }; + + anv_h265_matrix_from_uprightdiagonal(&out_sl, scaling_list); + /* 4x4, 8x8, 16x16, 32x32 */ for (uint8_t size = 0; size < 4; size++) { /* Intra, Inter */ @@ -89,22 +125,22 @@ for (uint8_t i = 0; i < 4; i++) for (uint8_t j = 0; j < 4; j++) qm.QuantizerMatrix8x8[4 * i + j] = - scaling_list->ScalingList4x4[3 * pred + color][4 * i + j]; + out_sl.ScalingList4x4[3 * pred + color][4 * i + j]; } else if (size == 1) { for (uint8_t i = 0; i < 8; i++) for (uint8_t j = 0; j < 8; j++) qm.QuantizerMatrix8x8[8 * i + j] = - scaling_list->ScalingList8x8[3 * pred + color][8 * i + j]; + out_sl.ScalingList8x8[3 * pred + color][8 * i + j]; } else if (size == 2) { for (uint8_t i = 0; i < 8; i++) for (uint8_t j = 0; j < 8; j++) qm.QuantizerMatrix8x8[8 * i + j] = - scaling_list->ScalingList16x16[3 * pred + color][8 * i + j]; + out_sl.ScalingList16x16[3 * pred + color][8 * i + j]; } else if (size == 3) { for (uint8_t i = 0; i < 8; i++) for (uint8_t j = 0; j < 8; j++) qm.QuantizerMatrix8x8[8 * i + j] = - scaling_list->ScalingList32x32[pred][8 * i + j]; + out_sl.ScalingList32x32[pred][8 * i + j]; } } } diff -Nru mesa-24.0.3/src/intel/vulkan/i915/anv_queue.c mesa-24.0.5/src/intel/vulkan/i915/anv_queue.c --- mesa-24.0.3/src/intel/vulkan/i915/anv_queue.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/vulkan/i915/anv_queue.c 2024-04-10 20:17:49.000000000 +0000 @@ -58,8 +58,13 @@ } else if (device->physical->has_vm_control) { assert(pCreateInfo->queueFamilyIndex < physical->queue.family_count); enum intel_engine_class engine_classes[1]; + enum intel_gem_create_context_flags flags = 0; + engine_classes[0] = queue_family->engine_class; - if (!intel_gem_create_context_engines(device->fd, 0 /* flags */, + if (pCreateInfo->flags & VK_DEVICE_QUEUE_CREATE_PROTECTED_BIT) + flags |= INTEL_GEM_CREATE_CONTEXT_EXT_PROTECTED_FLAG; + + if (!intel_gem_create_context_engines(device->fd, flags, physical->engine_info, 1, engine_classes, device->vm_id, @@ -74,7 +79,7 @@ queue_family->engine_class == INTEL_ENGINE_CLASS_COMPUTE) { uint32_t *context_id = (uint32_t *)&queue->companion_rcs_id; engine_classes[0] = INTEL_ENGINE_CLASS_RENDER; - if (!intel_gem_create_context_engines(device->fd, 0 /* flags */, + if (!intel_gem_create_context_engines(device->fd, flags, physical->engine_info, 1, engine_classes, device->vm_id, diff -Nru mesa-24.0.3/src/intel/vulkan/xe/anv_batch_chain.c mesa-24.0.5/src/intel/vulkan/xe/anv_batch_chain.c --- mesa-24.0.3/src/intel/vulkan/xe/anv_batch_chain.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/intel/vulkan/xe/anv_batch_chain.c 2024-04-10 20:17:49.000000000 +0000 @@ -114,9 +114,15 @@ struct drm_xe_sync **ret, uint32_t *ret_count) { struct anv_device *device = queue->device; - uint32_t num_syncs = wait_count + signal_count + extra_sync_count + - (utrace_submit ? 1 : 0) + - ((queue->sync && !is_companion_rcs_queue) ? 1 : 0); + /* Signal the utrace sync only if it doesn't have a batch. Otherwise the + * it's the utrace batch that should signal its own sync. + */ + const bool has_utrace_sync = utrace_submit && + util_dynarray_num_elements(&utrace_submit->batch_bos, struct anv_bo *) == 0; + const uint32_t num_syncs = wait_count + signal_count + extra_sync_count + + (has_utrace_sync ? 1 : 0) + + ((queue->sync && !is_companion_rcs_queue) ? 1 : 0); + if (!num_syncs) return VK_SUCCESS; @@ -128,12 +134,7 @@ uint32_t count = 0; - /* Signal the utrace sync only if it doesn't have a batch. Otherwise the - * it's the utrace batch that should signal its own sync. - */ - if (utrace_submit && - util_dynarray_num_elements(&utrace_submit->batch_bos, - struct anv_bo *) == 0) { + if (has_utrace_sync) { struct drm_xe_sync *xe_sync = &xe_syncs[count++]; xe_exec_fill_sync(xe_sync, utrace_submit->sync, 0, TYPE_SIGNAL); @@ -191,7 +192,7 @@ struct anv_queue *queue = submit->queue; struct anv_device *device = queue->device; struct anv_trtt *trtt = &device->trtt; - VkResult result; + VkResult result = VK_SUCCESS; struct drm_xe_sync extra_sync = { .type = DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, @@ -220,18 +221,22 @@ }; if (!device->info->no_hw) { - if (intel_ioctl(device->fd, DRM_IOCTL_XE_EXEC, &exec)) - return vk_device_set_lost(&device->vk, "XE_EXEC failed: %m"); + if (intel_ioctl(device->fd, DRM_IOCTL_XE_EXEC, &exec)) { + result = vk_device_set_lost(&device->vk, "XE_EXEC failed: %m"); + goto out; + } } if (queue->sync) { result = vk_sync_wait(&device->vk, queue->sync, 0, VK_SYNC_WAIT_COMPLETE, UINT64_MAX); if (result != VK_SUCCESS) - return vk_queue_set_lost(&queue->vk, "trtt sync wait failed"); + result = vk_queue_set_lost(&queue->vk, "trtt sync wait failed"); } - return VK_SUCCESS; +out: + vk_free(&device->vk.alloc, xe_syncs); + return result; } VkResult diff -Nru mesa-24.0.3/src/mesa/main/shaderapi.c mesa-24.0.5/src/mesa/main/shaderapi.c --- mesa-24.0.3/src/mesa/main/shaderapi.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/mesa/main/shaderapi.c 2024-04-10 20:17:49.000000000 +0000 @@ -2363,6 +2363,10 @@ GET_CURRENT_CONTEXT(ctx); struct gl_shader **sh; + /* no binary data can be loaded if length==0 */ + if (!length) + binary = NULL; + /* Page 68, section 7.2 'Shader Binaries" of the of the OpenGL ES 3.1, and * page 88 of the OpenGL 4.5 specs state: * diff -Nru mesa-24.0.3/src/mesa/main/teximage.c mesa-24.0.5/src/mesa/main/teximage.c --- mesa-24.0.3/src/mesa/main/teximage.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/mesa/main/teximage.c 2024-04-10 20:17:49.000000000 +0000 @@ -2472,6 +2472,15 @@ case GL_RGB10_A2: break; + case GL_RED: + case GL_RG: + /* GL_EXT_texture_rg adds support for GL_RED and GL_RG as an internal + * format + */ + if (_mesa_has_EXT_texture_rg(ctx)) + break; + + FALLTHROUGH; default: _mesa_error(ctx, GL_INVALID_ENUM, "glCopyTexImage%dD(internalFormat=%s)", dimensions, diff -Nru mesa-24.0.3/src/mesa/state_tracker/st_cb_copyimage.c mesa-24.0.5/src/mesa/state_tracker/st_cb_copyimage.c --- mesa-24.0.3/src/mesa/state_tracker/st_cb_copyimage.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/mesa/state_tracker/st_cb_copyimage.c 2024-04-10 20:17:49.000000000 +0000 @@ -282,7 +282,10 @@ blit.src.box = *src_box; u_box_3d(dstx, dsty, dstz, src_box->width, src_box->height, src_box->depth, &blit.dst.box); - blit.mask = PIPE_MASK_RGBA; + if (util_format_is_depth_or_stencil(dst_format)) + blit.mask = PIPE_MASK_ZS; + else + blit.mask = PIPE_MASK_RGBA; blit.filter = PIPE_TEX_FILTER_NEAREST; pipe->blit(pipe, &blit); diff -Nru mesa-24.0.3/src/mesa/state_tracker/st_context.c mesa-24.0.5/src/mesa/state_tracker/st_context.c --- mesa-24.0.3/src/mesa/state_tracker/st_context.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/mesa/state_tracker/st_context.c 2024-04-10 20:17:49.000000000 +0000 @@ -987,17 +987,17 @@ st_destroy_program_variants(st); - st_context_free_zombie_objects(st); - - simple_mtx_destroy(&st->zombie_sampler_views.mutex); - simple_mtx_destroy(&st->zombie_shaders.mutex); - /* Do not release debug_output yet because it might be in use by other threads. * These threads will be terminated by _mesa_free_context_data and * st_destroy_context_priv. */ _mesa_free_context_data(ctx, false); + st_context_free_zombie_objects(st); + + simple_mtx_destroy(&st->zombie_sampler_views.mutex); + simple_mtx_destroy(&st->zombie_shaders.mutex); + /* This will free the st_context too, so 'st' must not be accessed * afterwards. */ st_destroy_context_priv(st, true); diff -Nru mesa-24.0.3/src/mesa/state_tracker/st_format.c mesa-24.0.5/src/mesa/state_tracker/st_format.c --- mesa-24.0.3/src/mesa/state_tracker/st_format.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/mesa/state_tracker/st_format.c 2024-04-10 20:17:49.000000000 +0000 @@ -1333,6 +1333,21 @@ is_renderbuffer = true; } else { pTarget = gl_target_to_pipe(target); + if (internalFormat == format) { + if (internalFormat == GL_RGBA) { + /* with GL_RGBA, these are effectively aliases to required formats */ + switch (type) { + case GL_UNSIGNED_SHORT_5_5_5_1: + case GL_UNSIGNED_SHORT_4_4_4_4: + case GL_UNSIGNED_INT_8_8_8_8: + is_renderbuffer = true; + break; + default: break; + } + } else if (internalFormat == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5) { + is_renderbuffer = true; + } + } } if (target == GL_TEXTURE_1D || target == GL_TEXTURE_1D_ARRAY) { @@ -1351,7 +1366,9 @@ bindings = PIPE_BIND_SAMPLER_VIEW; if (_mesa_is_depth_or_stencil_format(internalFormat)) bindings |= PIPE_BIND_DEPTH_STENCIL; - else if (is_renderbuffer || internalFormat == 3 || internalFormat == 4 || + else if (is_renderbuffer) + bindings |= PIPE_BIND_RENDER_TARGET; + else if (internalFormat == 3 || internalFormat == 4 || internalFormat == GL_RGB || internalFormat == GL_RGBA || internalFormat == GL_RGBA2 || internalFormat == GL_RGB4 || internalFormat == GL_RGBA4 || diff -Nru mesa-24.0.3/src/mesa/state_tracker/st_pbo_compute.c mesa-24.0.5/src/mesa/state_tracker/st_pbo_compute.c --- mesa-24.0.3/src/mesa/state_tracker/st_pbo_compute.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/mesa/state_tracker/st_pbo_compute.c 2024-04-10 20:17:49.000000000 +0000 @@ -844,7 +844,7 @@ struct pbo_spec_async_data *spec; struct set_entry *entry = _mesa_set_search_or_add(&async->specialized, pd, &found); if (!found) { - spec = calloc(1, sizeof(struct pbo_async_data)); + spec = calloc(1, sizeof(struct pbo_spec_async_data)); util_queue_fence_init(&spec->fence); memcpy(spec->data, pd, sizeof(struct pbo_data)); entry->key = spec; diff -Nru mesa-24.0.3/src/nouveau/compiler/nak.h mesa-24.0.5/src/nouveau/compiler/nak.h --- mesa-24.0.3/src/nouveau/compiler/nak.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/nouveau/compiler/nak.h 2024-04-10 20:17:49.000000000 +0000 @@ -32,6 +32,8 @@ void nak_optimize_nir(nir_shader *nir, const struct nak_compiler *nak); void nak_preprocess_nir(nir_shader *nir, const struct nak_compiler *nak); +PRAGMA_DIAGNOSTIC_PUSH +PRAGMA_DIAGNOSTIC_ERROR(-Wpadded) struct nak_fs_key { bool zs_self_dep; @@ -40,6 +42,8 @@ */ bool force_sample_shading; + uint8_t _pad; + /** * The constant buffer index and offset at which the sample locations table lives. * Each sample location is two 4-bit unorm values packed into an 8-bit value @@ -48,6 +52,9 @@ uint8_t sample_locations_cb; uint32_t sample_locations_offset; }; +PRAGMA_DIAGNOSTIC_POP +static_assert(sizeof(struct nak_fs_key) == 8, "This struct has no holes"); + void nak_postprocess_nir(nir_shader *nir, const struct nak_compiler *nak, nir_variable_mode robust2_modes, diff -Nru mesa-24.0.3/src/nouveau/vulkan/nvk_cmd_buffer.c mesa-24.0.5/src/nouveau/vulkan/nvk_cmd_buffer.c --- mesa-24.0.3/src/nouveau/vulkan/nvk_cmd_buffer.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/nouveau/vulkan/nvk_cmd_buffer.c 2024-04-10 20:17:49.000000000 +0000 @@ -580,8 +580,13 @@ vk_to_nvk_descriptor_set_layout(pipeline_layout->set_layouts[set_idx]); if (desc->sets[set_idx] != set) { - desc->root.sets[set_idx] = nvk_descriptor_set_addr(set); - desc->set_sizes[set_idx] = set->size; + if (set != NULL) { + desc->root.sets[set_idx] = nvk_descriptor_set_addr(set); + desc->set_sizes[set_idx] = set->size; + } else { + desc->root.sets[set_idx] = 0; + desc->set_sizes[set_idx] = 0; + } desc->sets[set_idx] = set; desc->sets_dirty |= BITFIELD_BIT(set_idx); diff -Nru mesa-24.0.3/src/nouveau/vulkan/nvk_cmd_draw.c mesa-24.0.5/src/nouveau/vulkan/nvk_cmd_draw.c --- mesa-24.0.3/src/nouveau/vulkan/nvk_cmd_draw.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/nouveau/vulkan/nvk_cmd_draw.c 2024-04-10 20:17:49.000000000 +0000 @@ -3220,44 +3220,60 @@ bool inverted = pConditionalRenderingBegin->flags & VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT; - if (addr & 0x3f || buffer->is_local) { - uint64_t tmp_addr; - VkResult result = nvk_cmd_buffer_cond_render_alloc(cmd, &tmp_addr); - if (result != VK_SUCCESS) { - vk_command_buffer_set_error(&cmd->vk, result); - return; - } - - struct nv_push *p = nvk_cmd_buffer_push(cmd, 12); - P_MTHD(p, NV90B5, OFFSET_IN_UPPER); - P_NV90B5_OFFSET_IN_UPPER(p, addr >> 32); - P_NV90B5_OFFSET_IN_LOWER(p, addr & 0xffffffff); - P_NV90B5_OFFSET_OUT_UPPER(p, tmp_addr >> 32); - P_NV90B5_OFFSET_OUT_LOWER(p, tmp_addr & 0xffffffff); - P_NV90B5_PITCH_IN(p, 4); - P_NV90B5_PITCH_OUT(p, 4); - P_NV90B5_LINE_LENGTH_IN(p, 4); - P_NV90B5_LINE_COUNT(p, 1); - - P_IMMD(p, NV90B5, LAUNCH_DMA, { - .data_transfer_type = DATA_TRANSFER_TYPE_PIPELINED, - .multi_line_enable = MULTI_LINE_ENABLE_TRUE, - .flush_enable = FLUSH_ENABLE_TRUE, - .src_memory_layout = SRC_MEMORY_LAYOUT_PITCH, - .dst_memory_layout = DST_MEMORY_LAYOUT_PITCH, - }); - addr = tmp_addr; + /* From the Vulkan 1.3.280 spec: + * + * "If the 32-bit value at offset in buffer memory is zero, + * then the rendering commands are discarded, + * otherwise they are executed as normal." + * + * The hardware compare a 64-bit value, as such we are required to copy it. + */ + uint64_t tmp_addr; + VkResult result = nvk_cmd_buffer_cond_render_alloc(cmd, &tmp_addr); + if (result != VK_SUCCESS) { + vk_command_buffer_set_error(&cmd->vk, result); + return; } - struct nv_push *p = nvk_cmd_buffer_push(cmd, 12); + struct nv_push *p = nvk_cmd_buffer_push(cmd, 26); + + P_MTHD(p, NV90B5, OFFSET_IN_UPPER); + P_NV90B5_OFFSET_IN_UPPER(p, addr >> 32); + P_NV90B5_OFFSET_IN_LOWER(p, addr & 0xffffffff); + P_NV90B5_OFFSET_OUT_UPPER(p, tmp_addr >> 32); + P_NV90B5_OFFSET_OUT_LOWER(p, tmp_addr & 0xffffffff); + P_NV90B5_PITCH_IN(p, 4); + P_NV90B5_PITCH_OUT(p, 4); + P_NV90B5_LINE_LENGTH_IN(p, 4); + P_NV90B5_LINE_COUNT(p, 1); + + P_IMMD(p, NV90B5, SET_REMAP_COMPONENTS, { + .dst_x = DST_X_SRC_X, + .dst_y = DST_Y_SRC_X, + .dst_z = DST_Z_NO_WRITE, + .dst_w = DST_W_NO_WRITE, + .component_size = COMPONENT_SIZE_ONE, + .num_src_components = NUM_SRC_COMPONENTS_ONE, + .num_dst_components = NUM_DST_COMPONENTS_TWO, + }); + + P_IMMD(p, NV90B5, LAUNCH_DMA, { + .data_transfer_type = DATA_TRANSFER_TYPE_PIPELINED, + .multi_line_enable = MULTI_LINE_ENABLE_TRUE, + .flush_enable = FLUSH_ENABLE_TRUE, + .src_memory_layout = SRC_MEMORY_LAYOUT_PITCH, + .dst_memory_layout = DST_MEMORY_LAYOUT_PITCH, + .remap_enable = REMAP_ENABLE_TRUE, + }); + P_MTHD(p, NV9097, SET_RENDER_ENABLE_A); - P_NV9097_SET_RENDER_ENABLE_A(p, addr >> 32); - P_NV9097_SET_RENDER_ENABLE_B(p, addr & 0xfffffff0); + P_NV9097_SET_RENDER_ENABLE_A(p, tmp_addr >> 32); + P_NV9097_SET_RENDER_ENABLE_B(p, tmp_addr & 0xfffffff0); P_NV9097_SET_RENDER_ENABLE_C(p, inverted ? MODE_RENDER_IF_EQUAL : MODE_RENDER_IF_NOT_EQUAL); P_MTHD(p, NV90C0, SET_RENDER_ENABLE_A); - P_NV90C0_SET_RENDER_ENABLE_A(p, addr >> 32); - P_NV90C0_SET_RENDER_ENABLE_B(p, addr & 0xfffffff0); + P_NV90C0_SET_RENDER_ENABLE_A(p, tmp_addr >> 32); + P_NV90C0_SET_RENDER_ENABLE_B(p, tmp_addr & 0xfffffff0); P_NV90C0_SET_RENDER_ENABLE_C(p, inverted ? MODE_RENDER_IF_EQUAL : MODE_RENDER_IF_NOT_EQUAL); } diff -Nru mesa-24.0.3/src/nouveau/vulkan/nvk_shader.h mesa-24.0.5/src/nouveau/vulkan/nvk_shader.h --- mesa-24.0.3/src/nouveau/vulkan/nvk_shader.h 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/nouveau/vulkan/nvk_shader.h 2024-04-10 20:17:49.000000000 +0000 @@ -39,8 +39,10 @@ enum nvk_cbuf_type type; uint8_t desc_set; uint8_t dynamic_idx; + uint8_t _pad; uint32_t desc_offset; }; +static_assert(sizeof(struct nvk_cbuf) == 8, "This struct has no holes"); struct nvk_cbuf_map { uint32_t cbuf_count; diff -Nru mesa-24.0.3/src/panfrost/ci/panfrost-g52-fails.txt mesa-24.0.5/src/panfrost/ci/panfrost-g52-fails.txt --- mesa-24.0.3/src/panfrost/ci/panfrost-g52-fails.txt 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/panfrost/ci/panfrost-g52-fails.txt 2024-04-10 20:17:49.000000000 +0000 @@ -435,7 +435,6 @@ dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.int32,Crash dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.uint32,Crash -dEQP-VK.api.command_buffers.record_many_draws_secondary_2,Fail dEQP-VK.glsl.operator.sequence.no_side_effects.highp_bool_vec2_fragment,Fail dEQP-VK.glsl.operator.sequence.no_side_effects.highp_float_uint_fragment,Fail dEQP-VK.glsl.operator.sequence.no_side_effects.highp_vec4_ivec4_bvec4_fragment,Fail diff -Nru mesa-24.0.3/src/panfrost/vulkan/panvk_vX_cmd_buffer.c mesa-24.0.5/src/panfrost/vulkan/panvk_vX_cmd_buffer.c --- mesa-24.0.3/src/panfrost/vulkan/panvk_vX_cmd_buffer.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/panfrost/vulkan/panvk_vX_cmd_buffer.c 2024-04-10 20:17:49.000000000 +0000 @@ -532,6 +532,7 @@ pan_pack(attribs + offset, ATTRIBUTE, cfg) { cfg.buffer_index = first_buf + (img_idx + i) * 2; cfg.format = desc_state->sets[s]->img_fmts[i]; + cfg.offset_enable = false; } offset += pan_size(ATTRIBUTE); } diff -Nru mesa-24.0.3/src/panfrost/vulkan/panvk_vX_cs.c mesa-24.0.5/src/panfrost/vulkan/panvk_vX_cs.c --- mesa-24.0.3/src/panfrost/vulkan/panvk_vX_cs.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/panfrost/vulkan/panvk_vX_cs.c 2024-04-10 20:17:49.000000000 +0000 @@ -116,6 +116,7 @@ cfg.buffer_index = varyings->varying[loc].buf; cfg.offset = varyings->varying[loc].offset; cfg.format = panvk_varying_hw_format(dev, varyings, stage, idx); + cfg.offset_enable = false; } } @@ -286,6 +287,7 @@ pan_pack(attrib, ATTRIBUTE, cfg) { cfg.buffer_index = buf_idx * 2; cfg.offset = attribs->attrib[idx].offset + (bufs[buf_idx].address & 63); + cfg.offset_enable = true; if (buf_info->per_instance) cfg.offset += draw->first_instance * buf_info->stride; diff -Nru mesa-24.0.3/src/panfrost/vulkan/panvk_vX_meta_copy.c mesa-24.0.5/src/panfrost/vulkan/panvk_vX_meta_copy.c --- mesa-24.0.3/src/panfrost/vulkan/panvk_vX_meta_copy.c 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/panfrost/vulkan/panvk_vX_meta_copy.c 2024-04-10 20:17:49.000000000 +0000 @@ -82,6 +82,7 @@ pan_pack(varying.cpu, ATTRIBUTE, cfg) { cfg.buffer_index = 0; cfg.format = pool->dev->formats[PIPE_FORMAT_R32G32B32_FLOAT].hw; + cfg.offset_enable = false; } *varyings = varying.gpu; diff -Nru mesa-24.0.3/src/util/00-mesa-defaults.conf mesa-24.0.5/src/util/00-mesa-defaults.conf --- mesa-24.0.3/src/util/00-mesa-defaults.conf 2024-03-13 23:59:54.000000000 +0000 +++ mesa-24.0.5/src/util/00-mesa-defaults.conf 2024-04-10 20:17:49.000000000 +0000 @@ -431,6 +431,13 @@