Translate gate and pin names on Verilog export
Registered by
Danil Sokolov
On Verilog export enable substitution of gate and pin names to match the target library. The substitution rules should be read from an external file. The following format for a rule is suggested:
GATE_NAME=
Blueprint information
- Status:
- Complete
- Approver:
- None
- Priority:
- High
- Drafter:
- Danil Sokolov
- Direction:
- Needs approval
- Assignee:
- Danil Sokolov
- Definition:
- Approved
- Series goal:
- None
- Implementation:
-
Implemented
- Milestone target:
-
3.0.7
- Started by
- Danil Sokolov
- Completed by
- Danil Sokolov
Whiteboard
Example file of translation rules: DONE
Parser of the translation rules: DONE
Name substitution on export: DONE
(?)
