Import a Verilog netlist as a Circuit
Registered by
Danil Sokolov
Parse Verilog netlist (at least its subset used by Petrify) and create a corresponding Circuit model.
Blueprint information
- Status:
- Complete
- Approver:
- None
- Priority:
- Medium
- Drafter:
- Danil Sokolov
- Direction:
- Needs approval
- Assignee:
- Danil Sokolov
- Definition:
- Approved
- Series goal:
- None
- Implementation:
-
Implemented
- Milestone target:
-
3.0.5
- Started by
- Danil Sokolov
- Completed by
- Danil Sokolov
Whiteboard
(?)
Work Items
Work items:
Parser for standard structural Verilog: DONE
Parser for GenLib format: DONE
Parser for Petrify annotation of Verilog netlist (initial state, unmapped gates): DONE
Basic layouter for digital circuits: DONE
Composition of Verilog primitives into complex gates: DONE
Code refactoring: DONE
