Export from Digital Circuit model into Verilog netlist
Registered by
Danil Sokolov
An exporter tool
Two options are possibel:
Option 1 (simple): Generate a Verilog module for each complex gate found in a Digital Circuit model. Specify the behaviour of each gate using abstract Verilog primitives (buf, not, and, nand, or, nor, xor, xnor).
Option 2 (challenging): Map the complex gates of the Digital Circuit model into the supplied library of gates (in Verilog format). If no mapping is possible, then error out. The driving strength of the gates may also be taken into account.
Blueprint information
- Status:
- Complete
- Approver:
- Danil Sokolov
- Priority:
- Medium
- Drafter:
- Danil Sokolov
- Direction:
- Needs approval
- Assignee:
- Danil Sokolov
- Definition:
- Approved
- Series goal:
- None
- Implementation:
-
Implemented
- Milestone target:
-
3.0.5
- Started by
- Danil Sokolov
- Completed by
- Danil Sokolov
Whiteboard
(?)
Work Items
Work items:
Add "Module name" property to circuit components and to the Circuit model: DONE
Add wire names: DONE
Decompose unmapped gates into Verilog primitives: POSTPONED
