Verification for zero delay buffers and inverters
Registered by
Danil Sokolov
Add flag to circuit components to interpret them as zero delay elements. Adjust visualisation, simulation and verification accordingly.
Blueprint information
- Status:
- Complete
- Approver:
- None
- Priority:
- Low
- Drafter:
- Danil Sokolov
- Direction:
- Needs approval
- Assignee:
- Danil Sokolov
- Definition:
- Approved
- Series goal:
- None
- Implementation:
-
Implemented
- Milestone target:
-
3.0.6
- Started by
- Danil Sokolov
- Completed by
- Danil Sokolov
Whiteboard
(?)
Work Items
Work items:
Visualisation of zero-delay gates: DONE
Generating STG: DONE
Propagation of initial state: DONE
Restrictions on setting the zero-delay flag: DONE
Restrictions on connections: TODO
Simulation of zero-delay gates: TODO
