Calculate the initial state of signals on MPSat synthesis

When a circuit is imported from a Verilog netlist, the initial state of some signals may be defined by Petrify and MPSat in the comments. Currently MPSat does not define the state of internal signals. All signals whose state is undefined are initialised to 0. It would be better to calculate their real state (where possible).

This has been resolved on MPSat side - the state of all the signals is reported now.