Generate a list of relative timing assumptions for signoff
Registered by
Danil Sokolov
The following timing assumptions need to be checked in the final circuit:
* isochronic forks
* negligible delay inverters (input bubbles)
A set of SDC constraints need to be generated that can be used to assist the place-and-route and the timing analysis signoff.
Blueprint information
- Status:
- Not started
- Approver:
- None
- Priority:
- Medium
- Drafter:
- Danil Sokolov
- Direction:
- Needs approval
- Assignee:
- Danil Sokolov
- Definition:
- Approved
- Series goal:
- None
- Implementation:
-
Not started
- Milestone target:
- None
- Started by
- Completed by
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