PM Constraints: Intel
Power Management Constraints Topics:
1) Power vs. Performance
2) Priority Based PM QoS Constraints Framework
=== Welcome and Goals ===
Mark Gross
=== Power vs Performance ===
In order to suffice problems related to a "minimum" quality of service for basic HW like CPU/networking/DMA, we have the existing PM QoS framework to solve our problems. As the discrete HW units grow on a SoC, so IMO should the PM QoS layer scale.
The second part of the problem is the scaling "up" or "down". We can mirror the PM QoS constraints to Perf QoS constraints which would allow independent devices to scale the generic system upwards into the performance mode. The performance QoS can also be used by platform specific constraints like thermals to either throttle device/SoC features OR constraints like accelerated workloads that may require a minimal CPU/SoC operating point to scale SoC features.
Examples include issue faced on memory throughput on TI platforms, increasing CPU frequency as discussed in mailing lists by NVidia developers, imposing constraints on devices like CPU/LCD for thermal management etc.
Topic Lead: Sundar Iyer
Worked/Working on PM/tunings/
=== Intel SoC DVFS ===
DVFS implementations in hardware varry from CPU to CPU. We know that
some ARM only developers sometimes are confused as to how the intel
parts implement DVFS and how it differs from the chips they know about.
To provide some intuition on how DVFS works on Intel SOC's we provide a
short slide deck outlining the core ideas that hopefully provide insight
as to why the intel derived power management code in the Linux kernel is
the way it is.
Topic Lead: Mark Gross