Study: Tool for runtime visualisation of clocks and regulators

Registered by Amit Kucheria

* Allow developers to see a clock sub-tree or regulator sub-tree
* Display updates at runtime

Blueprint information

Status:
Complete
Approver:
Amit Kucheria
Priority:
High
Drafter:
Amit Kucheria
Direction:
Approved
Assignee:
Yong
Definition:
Approved
Series goal:
Accepted for 11.05
Implementation:
Implemented
Milestone target:
milestone icon 11.05-final
Started by
Amit Kucheria
Completed by
Amit Kucheria

Related branches

Sprints

Whiteboard

Status:
Done

[amitk: post LDS 4/11/2010]
 * Clock debug info is being handled in a separate blueprint (https://blueprints.launchpad.net/linaro-pm-wg/+spec/clock-framework-debug)

[yong: pre LDS topics]

Questions needs to be answered:
1. How to show clock names? Currently there are two types of names: connection name and device name. I assume in one system each clock should have an unique name, which makes it possible to build up a clock tree. So we also should impose this principle to clock drivers. We can choose a clock name displayed in clock tree like "dev_name-con-name" and make it unique by add some name checking code in clk_add() interface. Any new ideas?
The solution to this is that jeremy will add a common struct clk with name field inside.

2. debug vs sysfs
After some research, I personally agree debug over sysfs. First of all, its purpose is for device driver development or system tuning, therefore it makes sense to put it in debug fs and don't compile in all the time. Moreover, debugfs is light weight and easy to use, which is already used in omap clock information interface.

3. More features
Many fellows want more features in this clk informantion system, like RW attribute or whatever. However, the first step is to make the system work, and then add more features.

4. Unified interface vs platform related interface
Adding a unified interface in common clk framework to support this feather could bring benefit all SOCs. It's better than implementing this on each individual SOC, like omap has its own clock debug interface and freescale has another one. I assume this is the purpose of Linaro project.

(?)

Work Items

Work items:
[amitarora] powerdebug: Add support to display clock tree from debugfs: DONE
[yong.shen] Discuss with amitarora about the kernel interface of clock information: DONE
[yong.shen] Investigate the design which have already been there: DONE
[yong.shen] get basic runtime regulator information into powerdebug (similar to clock info): DONE
[yong.shen] upstream pmic driver which is needed for powerdebug testing (in maintainer's tree): DONE

Dependency tree

* Blueprints in grey have been implemented.

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