Improve extraction of vectors from strided loads

Registered by Richard Sandiford on 2011-09-07

Before reload, we use separate rtl moves to extract each vector
from the result of a strided load. These moves have a subreg source
and a reg destination. We want the register allocator to turn these moves
into nops, and it in many cases it does. However:

  1) in functions with rather high register pressure, these extra temporary
      registers seem to tip the balance in favour of spilling

  2) These moves disrupt the pre-reload schedulers (including SMS).

Propogating the subreg into the point of use avoids both problems and
appears to generate better code. It will need wider testing though.

Status:

Patch for fwprop.c posted for comments upstream and seemed to receive positive feedback. ARM patch applied upstream. Need to do some benchmarking on other targets before posting the fwprop.c patch for approval. Current patch posted here:

    http://lists.linaro.org/pipermail/linaro-toolchain/2011-December/001946.html

Blueprint information

Status:
Complete
Approver:
Michael Hope
Priority:
Medium
Drafter:
Richard Sandiford
Direction:
Approved
Assignee:
Ulrich Weigand
Definition:
Approved
Series goal:
Accepted for 4.6
Implementation:
Implemented
Milestone target:
milestone icon 4.7-2012.04
Started by
Michael Hope on 2011-09-07
Completed by
Ulrich Weigand on 2012-04-10

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