Improve generation of conditional execution instructions

Registered by Ramana Radhakrishnan on 2011-08-24

Improve conditional execution code generation (cond-exec) especially for store-flag sequences. This is in the cases that we compare values with 0 or with other registers. It might be possible to improve these in certain cases to avoid conditional instructions and replace them with equivalent arithmetic instructions. The changes will be in the backend areas and potentially.

Blueprint information

Status:
Complete
Approver:
Matthew Gretton-Dann
Priority:
High
Drafter:
Ramana Radhakrishnan
Direction:
Approved
Assignee:
Zhenqiang Chen
Definition:
Approved
Series goal:
Accepted for 4.8
Implementation:
Informational Informational
Milestone target:
milestone icon 4.8-2013.09
Started by
Matthew Gretton-Dann on 2013-02-04
Completed by
Matthew Gretton-Dann on 2013-05-21

Related branches

Sprints

Whiteboard

[2013-05-21 matthew-gretton-dann] This blueprint has moved into Jira: http://cards.linaro.org/browse/TCWG-10.

[matthew-gretton-dann 2013-03-20] Investigations show that LOGICAL_OP_NON_SHORT_CIRCUIT does not provide the benefit desired.

[matthew-gretton-dann] Initial phase is to play with LOGICAL_OP_NON_SHORT_CIRCUIT being always true, and what happens to benchmarks as we vary branch costs.

Meta:
Headline: Improve generation of Conditional instructions for ARM
Acceptance: Patches accepted upstream and backported into Linaro GCC
Roadmap id: CARD-304

(?)

Work Items

Work items:
Investigate tuning of logical short circuit op and branch cost:: DONE
Add new tree level ops (CMP_OP_COND_AND, CMP_OP_COND_OR):: DONE
Expand to current code:: DONE
Handle conditional compare in vrp pass:: DONE
Handle conditional compare in uninit pass:: DONE
Handle conditional compare in reassoc1, dom1, dom2 and dce:: TODO
Discuss with upstream:: TODO
Add new expansions to generate optimised code:: TODO

Dependency tree

* Blueprints in grey have been implemented.

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